一个21mW 8b 125MS/s ADC，占用0.09mm/sup / / 0.13/spl mu/m CMOS

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332693

J. Mulder, C. Ward, Chi-Hung Lin, D. Kruse, J. Westra, M. Lugthart, E. Arslan, R. van de Plassche, K. Bult, F.M.L. van der Goes

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引用次数: 3

摘要

8b分位ADC采用插值、平均、偏移补偿和流水线技术，以125MS/s的速度实现7.6b ENOB。0.13/spl mu/m的CMOS ADC占用0.09mm/sup /，功耗21 mW。

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A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13/spl mu/m CMOS

An 8b subranging ADC uses interpolation, averaging, offset compensation and pipelining techniques to accomplish 7.6b ENOB at 125MS/s. The 0.13/spl mu/m CMOS ADC occupies 0.09mm/sup 2/ and consumes 21 mW.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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