一个PVT容忍度为0.18MHz至600MHz的90nm CMOS工艺自校准数字锁相环

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332807

J. Lin, B. Haroun, T. Foo, Jin-Sheng Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, J. Kirkpatric

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引用次数: 102

摘要

本文提出了一种具有对数时间数字化仪、数控振荡器和启动校准的数字锁相环，在0.18 MHz ~ 600 MHz的输出频率和PVT条件下实现了恒定的阻尼因子和分数环带宽，输出抖动小于0.04 UIPP。这款0.18 mm/sup /芯片采用90 nm CMOS，工作电源范围为0.7至2.4 V，在1 V和520 MHz下功耗为1.7 mW。

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A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process

This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm/sup 2/ chip is implemented in 90 nm CMOS, operates over a 0.7 to 2.4 V power supply range and consumes 1.7 mW at 1 V and 520 MHz.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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