具有率失真优化的81MS/s JPEG2000单片机编码器

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332727

Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian, Liang-Gee Chen

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引用次数: 35

摘要

采用0.25/spl mu/m CMOS技术，在5.5mm/sup / 2/芯片上实现了81MS/s的JPEG 2000单片机编码器。该集成电路可以实时编码30帧/秒的高清电视720p分辨率。经过率失真优化的芯片编码的tile大小为128/spl times/128，代码块大小为64/spl times/64，图像大小为32K/spl times/32K。

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81MS/s JPEG2000 single-chip encoder with rate-distortion optimization

An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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