M. Iwatal, M. Ogura, Y. Ohishi, H. Hayashi, H. Terada
{"title":"100mppackets /s完全自定时优先队列:FQ","authors":"M. Iwatal, M. Ogura, Y. Ohishi, H. Hayashi, H. Terada","doi":"10.1109/ISSCC.2004.1332638","DOIUrl":null,"url":null,"abstract":"This priority queuing module is integrated as part of QoS functions in a data-driven network processor chip. Since the whole FQ circuit is realized by a fully self-timed folded pipeline, each prioritized 128b packet arriving at 100Mpackets/s is queued and scheduled autonomously in a self-timed manner.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"100MPackets/s fully self-timed priority queue: FQ\",\"authors\":\"M. Iwatal, M. Ogura, Y. Ohishi, H. Hayashi, H. Terada\",\"doi\":\"10.1109/ISSCC.2004.1332638\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This priority queuing module is integrated as part of QoS functions in a data-driven network processor chip. Since the whole FQ circuit is realized by a fully self-timed folded pipeline, each prioritized 128b packet arriving at 100Mpackets/s is queued and scheduled autonomously in a self-timed manner.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"116 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332638\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332638","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This priority queuing module is integrated as part of QoS functions in a data-driven network processor chip. Since the whole FQ circuit is realized by a fully self-timed folded pipeline, each prioritized 128b packet arriving at 100Mpackets/s is queued and scheduled autonomously in a self-timed manner.