具有两个多媒体dsp和用于视频压缩应用的RISC核心的SoC

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332728

H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch

{"title":"具有两个多媒体dsp和用于视频压缩应用的RISC核心的SoC","authors":"H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch","doi":"10.1109/ISSCC.2004.1332728","DOIUrl":null,"url":null,"abstract":"An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"An SoC with two multimedia DSPs and a RISC core for video compression applications\",\"authors\":\"H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch\",\"doi\":\"10.1109/ISSCC.2004.1332728\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332728\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 26

摘要

SoC由一个带有2D矩阵存储器的16路SIMD DSP内核、一个具有子字并行性的64b VLIW DSP内核和一个32b RISC内核组成。81mm/sup 2/芯片采用0.18/spl mu/m 6M标准单元技术，运行频率为145MHz。该设备可以进行D1分辨率的MPEG-4高级简单配置文件解码、MPEG-4编码和实时目标分割。

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An SoC with two multimedia DSPs and a RISC core for video compression applications

An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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