{"title":"81MS/s JPEG2000 single-chip encoder with rate-distortion optimization","authors":"Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian, Liang-Gee Chen","doi":"10.1109/ISSCC.2004.1332727","DOIUrl":null,"url":null,"abstract":"An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332727","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35
Abstract
An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.