用于高速DRAM的3.6 Gb/s/pin同步双向(SBD) I/O接口

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332770

Jaekwan Kim, J. Choi, Sungcheol Shin, Chan-Kyong Kim, Hwa-Yong Kim, Woo-Seop Kim, Chan-Kyong Kim, Sooin Cho

{"title":"用于高速DRAM的3.6 Gb/s/pin同步双向(SBD) I/O接口","authors":"Jaekwan Kim, J. Choi, Sungcheol Shin, Chan-Kyong Kim, Hwa-Yong Kim, Woo-Seop Kim, Chan-Kyong Kim, Sooin Cho","doi":"10.1109/ISSCC.2004.1332770","DOIUrl":null,"url":null,"abstract":"A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 /spl mu/m DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM\",\"authors\":\"Jaekwan Kim, J. Choi, Sungcheol Shin, Chan-Kyong Kim, Hwa-Yong Kim, Woo-Seop Kim, Chan-Kyong Kim, Sooin Cho\",\"doi\":\"10.1109/ISSCC.2004.1332770\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 /spl mu/m DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332770\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

描述了一种用于高速DRAM的点对点I/O接口。该接口采用同步双向信令，允许通过一条线路同时发送/接收数据。测试方案在0.10 /spl mu/m DRAM进程中实现。它在SBD模式下达到3.6 Gb/s/引脚，一个I/O单元消耗35 mW。

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A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM

A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 /spl mu/m DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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