{"title":"实现了包含400个独立的低功耗、高线性度定时游标的量产ATE定制处理器和定时IC","authors":"B. Arkin","doi":"10.1109/ISSCC.2004.1332737","DOIUrl":null,"url":null,"abstract":"An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers\",\"authors\":\"B. Arkin\",\"doi\":\"10.1109/ISSCC.2004.1332737\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332737\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332737","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers
An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.