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2012 Symposium on VLSI Technology (VLSIT)最新文献

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Near-field wireless connection for 3D-system integration 用于3d系统集成的近场无线连接
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242483
T. Kuroda
{"title":"Near-field wireless connection for 3D-system integration","authors":"T. Kuroda","doi":"10.1109/VLSIT.2012.6242483","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242483","url":null,"abstract":"This paper describes a wireless inter-chip link using inductive coupling, namely ThruChip Interface (TCI). TCI is a digital CMOS circuit solution in a standard CMOS technology. It is less expensive than TSV but bears comparison in performance.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory 三层TaOx RRAM的多级开关，具有优异的可靠性，用于存储级存储器
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242466
Seung Ryul Lee, Young-Bae Kim, Man Chang, K. Kim, Chang Bum Lee, J. Hur, G. Park, Dongsoo Lee, Myoung-Jae Lee, C. J. Kim, U. Chung, I. Yoo, Kinam Kim
{"title":"Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory","authors":"Seung Ryul Lee, Young-Bae Kim, Man Chang, K. Kim, Chang Bum Lee, J. Hur, G. Park, Dongsoo Lee, Myoung-Jae Lee, C. J. Kim, U. Chung, I. Yoo, Kinam Kim","doi":"10.1109/VLSIT.2012.6242466","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242466","url":null,"abstract":"A highly reliable RRAM with multi-level cell (MLC) characteristics were fabricated using a triple-layer structure (base layer/oxygen exchange layer/barrier layer) for the storage class memory applications. A reproducible multi-level switching behaviour was successfully observed, and simulated by the modulated Schottky barrier model. Morevoer, a new programming algorithm was developed for more reliable and uniform MLC operation. As a result, more than 107 cycles of switching endurance and 10 years of data retention at 85°C for all the 2 bit/cell operation were archieved.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 147
Field-driven ultrafast sub-ns programming in WAl2O3TiCuTe-based 1T1R CBRAM system 基于WAl2O3Ti cute的1T1R CBRAM系统的场驱动超快子ns编程
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242465
L. Goux, K. Sankaran, G. Kar, N. Jossart, K. Opsomer, R. Degraeve, G. Pourtois, G. Rignanese, C. Detavernier, S. Clima, Y. Chen, A. Fantini, B. Govoreanu, D. Wouters, M. Jurczak, L. Altimime, J. Kittl
{"title":"Field-driven ultrafast sub-ns programming in WAl2O3TiCuTe-based 1T1R CBRAM system","authors":"L. Goux, K. Sankaran, G. Kar, N. Jossart, K. Opsomer, R. Degraeve, G. Pourtois, G. Rignanese, C. Detavernier, S. Clima, Y. Chen, A. Fantini, B. Govoreanu, D. Wouters, M. Jurczak, L. Altimime, J. Kittl","doi":"10.1109/VLSIT.2012.6242465","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242465","url":null,"abstract":"We optimize a 90nm-wide CuTe-based 1T1R CBRAM cell for highly controlled and ultrafast programming by engineering Al2O3 electrolyte and Ti buffer layers of appropriate density and thickness resp. By means of electrical and ab initio modeling, we demonstrate that switching is mainly controlled by field-driven motion of Cu+ species. Sub-ns programming is allowed by strong ionic-hopping barrier reduction over short insulating gap. Complete picture of conductance and switching phenomenology is shown in the entire operation range.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"38 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133733201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Antimonide NMOSFET with source side injection velocity of 2.7×107 cm/s for low power high performance logic applications 源侧注入速度为2.7×107 cm/s的锑化NMOSFET，适用于低功耗高性能逻辑应用
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242521
A. Ali, H. Madan, M. Barth, M. Hollander, J. B. Boos, B. R. Bennett, S. Datta
{"title":"Antimonide NMOSFET with source side injection velocity of 2.7×107 cm/s for low power high performance logic applications","authors":"A. Ali, H. Madan, M. Barth, M. Hollander, J. B. Boos, B. R. Bennett, S. Datta","doi":"10.1109/VLSIT.2012.6242521","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242521","url":null,"abstract":"Antimonide (Sb) quantum well (QW) MOSFETs are demonstrated with integrated high-κ dielectric (1nmAl<sub>2</sub>O<sub>3</sub>-10nm HfO<sub>2</sub>). The long channel Sb NMOS exhibits effective electron mobility of 6,000 cm<sup>2</sup>/Vs at high field (2 × 10<sup>12</sup> /cm<sup>2</sup> of charge density (N<sub>s</sub>)), which is the highest reported value for any III-V MOSFET. The short channel Sb NMOSFET (L<sub>G</sub> = 150nm) exhibits a cut-off frequency (f<sub>T</sub>) of 120GHz, f<sub>T</sub> - L<sub>G</sub> product of 18GHz.μm and source side injection velocity (v<sub>eff</sub>) of 2.7×10<sup>7</sup> cm/s, at drain bias (V<sub>DS</sub>) of 0.75V and gate overdrive of 0.6V. The measured f<sub>T</sub> and f<sub>T</sub> × L<sub>G</sub> are 2 x higher, and v<sub>eff</sub> is 4× higher than Si NMOS (1.0-1.2V V<sub>DD</sub>) at similar L<sub>G</sub>, and are the highest for any III-V MOSFET.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128161416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
28nm FDSOI technology platform for high-speed low-voltage digital applications 28nm FDSOI技术平台，适用于高速低压数字应用
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242497
N. Planes, Olivier Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. Sassoulas, Xavier Federspiel, Antoine Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, David Petit, D. Golanski, C. Fenouillet-Béranger, N. Guillot, M. Rafik, Vincent Huard, S. Puget, X. Montagner, M. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, Michel Haond
{"title":"28nm FDSOI technology platform for high-speed low-voltage digital applications","authors":"N. Planes, Olivier Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. Sassoulas, Xavier Federspiel, Antoine Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, David Petit, D. Golanski, C. Fenouillet-Béranger, N. Guillot, M. Rafik, Vincent Huard, S. Puget, X. Montagner, M. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, Michel Haond","doi":"10.1109/VLSIT.2012.6242497","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242497","url":null,"abstract":"For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130494487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 401
Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS 应变工程超薄SOI (ETSOI)用于高性能CMOS
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242489
A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, P. Kulkarni, Q. Liu, P. Hashemi, P. Khare, S. Luning, S. Mehta, J. Gimbert, Y. Zhu, Z. Zhu, J. Li, A. Madan, T. Levin, F. Monsieur, T. Yamamoto, S. Naczas, S. Schmitz, S. Holmes, C. Aulnette, N. Daval, W. Schwarzenbach, B. Nguyen, V. Paruchuri, M. Khare, G. Shahidi, B. Doris
{"title":"Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS","authors":"A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, P. Kulkarni, Q. Liu, P. Hashemi, P. Khare, S. Luning, S. Mehta, J. Gimbert, Y. Zhu, Z. Zhu, J. Li, A. Madan, T. Levin, F. Monsieur, T. Yamamoto, S. Naczas, S. Schmitz, S. Holmes, C. Aulnette, N. Daval, W. Schwarzenbach, B. Nguyen, V. Paruchuri, M. Khare, G. Shahidi, B. Doris","doi":"10.1109/VLSIT.2012.6242489","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242489","url":null,"abstract":"High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and I<sub>eff</sub> of 0.95mA/μm and 0.70mA/μm at I<sub>off</sub> =100nA/μm and V<sub>DD</sub> of 1V, for NFET and PFET, respectively.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127636630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Intrinsic fluctuations in Vertical NAND flash memories 垂直NAND快闪记忆体的内在波动
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242441
E. Nowak, Jae-ho Kim, Hyeyoung Kwon, Young-Gu Kim, J. Sim, Seung-Hyun Lim, Dae Sin Kim, Keun-Ho Lee, Young-Kwan Park, Jeong-Hyuk Choi, C. Chung
{"title":"Intrinsic fluctuations in Vertical NAND flash memories","authors":"E. Nowak, Jae-ho Kim, Hyeyoung Kwon, Young-Gu Kim, J. Sim, Seung-Hyun Lim, Dae Sin Kim, Keun-Ho Lee, Young-Kwan Park, Jeong-Hyuk Choi, C. Chung","doi":"10.1109/VLSIT.2012.6242441","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242441","url":null,"abstract":"Vertical NAND (VNAND) technology relies on polysilicon for channel material. Two intrinsic variation sources of the cell threshold voltage induced by polysilicon traps have been identified and simulated: Random Trap Fluctuation (RTF) and Random Telegraph Noise (RTN). We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of VT distribution for VNAND devices in MLC operation.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications 三维存储/逻辑应用中使用无凹凸互连的超薄片上晶圆工艺的发展
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242516
N. Maeda, H. Kitada, K. Fujimoto, Y. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, T. Ohba
{"title":"Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications","authors":"N. Maeda, H. Kitada, K. Fujimoto, Y. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, T. Ohba","doi":"10.1109/VLSIT.2012.6242516","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242516","url":null,"abstract":"Chip-on-Wafer (COW) stacking structure using stack-first and bumpless interconnects was successfully fabricated for the first time. Chips were arrayed and bonded onto the wafer by back-to-face and gap filling between chips were carried out using organic material without void formation. Chips on the wafer were thinned down to 5 μm. Via-holes were formed at off-chip area (outside the chip). Copper redistribution line was formed using the via-first Damascene method. Lower leakage current as low as back ground was found between pads. No failure and an approximate 100% yield were achieved in the vertical wiring for multi-chips COW stacking.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116656723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hybrid memory cube new DRAM architecture increases density and performance 混合内存立方体新的DRAM架构提高密度和性能
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242474
Joe M. Jeddeloh, B. Keeth
{"title":"Hybrid memory cube new DRAM architecture increases density and performance","authors":"Joe M. Jeddeloh, B. Keeth","doi":"10.1109/VLSIT.2012.6242474","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242474","url":null,"abstract":"Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 410
10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and Vth tunability through thin BOX 10nm直径的三栅极硅纳米线mosfet具有增强的高场输运和Vth可调谐性
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242436
M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata
{"title":"10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and Vth tunability through thin BOX","authors":"M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata","doi":"10.1109/VLSIT.2012.6242436","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242436","url":null,"abstract":"We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with Vth tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and Ion of 1mA/μm at Ioff of 100nA/μm is achieved. We also demonstrate Vth control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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