混合内存立方体新的DRAM架构提高密度和性能

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242474

Joe M. Jeddeloh, B. Keeth

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引用次数: 410

摘要

多核处理器的性能受到存储系统带宽的限制。混合内存立方体是一种三维DRAM架构，可以改善延迟、带宽、功耗和密度。通过硅通孔(tsv)， 3D封装和先进的CMOS性能使存储器系统架构的新方法。异质晶片堆叠有更多的连接，从而减少了信号传播的距离。

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Hybrid memory cube new DRAM architecture increases density and performance

Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.

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2012 Symposium on VLSI Technology (VLSIT)

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