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2012 Symposium on VLSI Technology (VLSIT)最新文献

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Continuous characterization of MOSFET from low-frequency noise to thermal noise using a novel measurement system up to 100 MHz 使用高达100 MHz的新型测量系统对MOSFET进行从低频噪声到热噪声的连续表征
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242502
K. Ohmori, R. Hasunuma, W. Feng, K. Yamada
{"title":"Continuous characterization of MOSFET from low-frequency noise to thermal noise using a novel measurement system up to 100 MHz","authors":"K. Ohmori, R. Hasunuma, W. Feng, K. Yamada","doi":"10.1109/VLSIT.2012.6242502","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242502","url":null,"abstract":"We have developed a novel system for characterizing higher-frequency noise properties of MOSFETs under DC-biases up to 100 MHz. A low-noise amplifier (LNA) was mounted on a unique micro probe-card so that the signal from DUT (on a wafer) is captured with lesser losses. Using this new approach, we have successfully demonstrated the transition of low-frequency (LF) noise to high-frequency (HF) noise, such as thermal noise. In addition, the change in the factors of noise results in lowing the standard variation of noise in a HF region, where intrinsic phenomena derived from the channel conductance play a key roll.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125159384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sub-fM DNA sensitivity by self-aligned maskless thin-film transistor-based SoC bioelectronics 基于自对准无掩膜薄膜晶体管的SoC生物电子学的亚fm DNA灵敏度
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242494
Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, F. Hsueh, Wen-Hsien Huang, Yu-Chung Lien, Hsiu-Chih Chen, Hsiao-Ting Hsueh, Che-Wei Huang, Chih-Ting Lin, Yin-Chih Liu, Ta-Hsien Lee, M. Hua, J. Qiu, Mao-Chen Liu, Yao-Jen Lee, J. Shieh, C. Ho, C. Hu, Fu-Liang Yang
{"title":"Sub-fM DNA sensitivity by self-aligned maskless thin-film transistor-based SoC bioelectronics","authors":"Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, F. Hsueh, Wen-Hsien Huang, Yu-Chung Lien, Hsiu-Chih Chen, Hsiao-Ting Hsueh, Che-Wei Huang, Chih-Ting Lin, Yin-Chih Liu, Ta-Hsien Lee, M. Hua, J. Qiu, Mao-Chen Liu, Yao-Jen Lee, J. Shieh, C. Ho, C. Hu, Fu-Liang Yang","doi":"10.1109/VLSIT.2012.6242494","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242494","url":null,"abstract":"This is the first study to successfully achieve record DNA sensitivity (sub-fM) by self-aligned, maskless, dual-channel, and metal-gate-based thin-film transistor nano-wire FET. Both novel device architecture (dual-channel) and optimization of integration processes (microcrystalline silicon and self-aligned sidewall sub-50 nm critical dimension) of nano-wire FET enhance the sensitivity to biological entities substantially. Meanwhile, the proposed device is accomplished with an embedded VLSI CMOS circuit. It can thus offer high application potential to pH, protein, and DNA probing in SoC-based portable bioelectronics.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction 采用III-V纳米线/硅异质结的陡坡隧道场效应晶体管
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242454
K. Tomioka, M. Yoshimura, T. Fukui
{"title":"Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction","authors":"K. Tomioka, M. Yoshimura, T. Fukui","doi":"10.1109/VLSIT.2012.6242454","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242454","url":null,"abstract":"In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126773715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 151
A novel chemically, thermally and electrically robust Cu interconnect structure with an organic non-porous ultralow-k dielectric fluorocarbon (k=2.2) 一种具有有机无孔超低k介电碳碳化合物(k=2.2)的新型化学、热、电稳定性强的Cu互连结构
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242490
X. Gu, A. Teramoto, R. Kuroda, Y. Tomita, T. Nemoto, S. Kuroki, S. Sugawa, T. Ohmi
{"title":"A novel chemically, thermally and electrically robust Cu interconnect structure with an organic non-porous ultralow-k dielectric fluorocarbon (k=2.2)","authors":"X. Gu, A. Teramoto, R. Kuroda, Y. Tomita, T. Nemoto, S. Kuroki, S. Sugawa, T. Ohmi","doi":"10.1109/VLSIT.2012.6242490","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242490","url":null,"abstract":"A novel chemically, thermally and electrically robust Cu damascene interconnects with an organic non-porous ultralow-k (ULK) dielectric fluorocarbon (k=2.2), deposited by an advanced microwave excited plasma enhanced CVD, is demonstrated. A practical nitrogen plasma treatment (NPT) was employed to minimize chemically damage introduction to fluorocarbon in post-etching cleaning and CMP processes. Also, a new structure with a delamination-protective-liner (DPL), instead of barrier-metal, between Cu and fluorocarbon is introduced to avoid thermally induced electrical degradation and to reduce the interconnect delay significantly (by >;30% in 32 nm-node). Non-porous ULK fluorocarbon with NPT and DPL technologies is a promising candidate for high performance Cu interconnects.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"20 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129027565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer 具有低温N+/P结形成和GeSnO2界面层的应变锗锡(GeSn) N沟道mosfet
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242479
G. Han, S. Su, Lanxiang Wang, Wei Wang, X. Gong, Yue Yang, Ivana, P. Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, C. Xue, B. Cheng, Y. Yeo
{"title":"Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer","authors":"G. Han, S. Su, Lanxiang Wang, Wei Wang, X. Gong, Yue Yang, Ivana, P. Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, C. Xue, B. Cheng, Y. Yeo","doi":"10.1109/VLSIT.2012.6242479","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242479","url":null,"abstract":"In this paper, we report the world's first germanium-tin (GeSn) channel nMOSFETs. Highlights of process module advances are: low temperature (400 °C) process for forming high quality n+/p junction with high dopant activation and reduced dopant diffusion; interface engineering achieved with GeSnO2 interfacial layer (IL) between high-k gate dielectric and GeSn channel. A gate-last process was employed. The GeSn nMOSFET with GeSnO2 IL demonstrates a substantially improved SS in comparison with Ge control, and an ION/IOFF ratio of 104.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation 采用等离子体后氧化制备HfO2/Al2O3/GeOx/Ge栅极堆，具有0.7 nm超薄EOT的高迁移率Ge pmosfet
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242511
R. Zhang, P. Huang, N. Taoka, M. Takenaka, S. Takagi
{"title":"High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation","authors":"R. Zhang, P. Huang, N. Taoka, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2012.6242511","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242511","url":null,"abstract":"HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/GeO<sub>x</sub>/Ge gate stacks were fabricated by applying the plasma post oxidation to HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/Ge structures. These Ge gate stack are shown to simultaneously realize both ultrathin EOT of ~0.7 nm and low D<sub>it</sub> of 10<sup>11</sup> cm<sup>-2</sup>eV<sup>-1</sup> order. The superior operation of (100) Ge pMOSFETs with these gate stacks has been demonstrated with record high hole mobility of 596 cm<sup>2</sup>/Vs under ~0.8 nm EOT among the Ge pMOSFETs reported so far.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124668128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL) 由一种新型自对准独立控制双栅串选择晶体管(SSL)解码的高间距可伸缩3D垂直栅(VG) NAND闪存
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242476
Chih-Ping Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Shih-Hung Chen, Y. Shih, K. Hsieh, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
{"title":"A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)","authors":"Chih-Ping Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Shih-Hung Chen, Y. Shih, K. Hsieh, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/VLSIT.2012.6242476","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242476","url":null,"abstract":"Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123997000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
High-aspect ratio through silicon via (TSV) technology 高纵横比通过硅通孔(TSV)技术
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242517
H. B. Chang, H. Y. Chen, P. Kuo, C. H. Chien, E. Liao, T. Lin, T. S. Wei, Y. Lin, Y. H. Chen, K. Yang, H. A. Teng, W. Tsai, Y. Tseng, S. Y. Chen, C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, S. Hou, W. Chiou, S. Jeng, C. H. Yu
{"title":"High-aspect ratio through silicon via (TSV) technology","authors":"H. B. Chang, H. Y. Chen, P. Kuo, C. H. Chien, E. Liao, T. Lin, T. S. Wei, Y. Lin, Y. H. Chen, K. Yang, H. A. Teng, W. Tsai, Y. Tseng, S. Y. Chen, C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, S. Hou, W. Chiou, S. Jeng, C. H. Yu","doi":"10.1109/VLSIT.2012.6242517","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242517","url":null,"abstract":"The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121681712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology 一种新颖的低阻栅极填充物，用于20nm及以上栅极长度缩放，用于栅极末高k/金属栅极CMOS技术
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242445
U. Kwon, K. Wong, S. Krishnan, L. Econimikos, X. Zhang, C. Ortolland, L. Thanh, J. Laloe, J. Huang, L. Edge, H. M. Wang, M. Gribelyuk, D. Rath, R. Bingert, Y. Liu, R. Bao, I. Kim, R. Ramachandran, W. Lai, J. Cutler, D. S. Salvador, Y. Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R. Divakaruni, X. Chen, M. Chudzik
{"title":"A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology","authors":"U. Kwon, K. Wong, S. Krishnan, L. Econimikos, X. Zhang, C. Ortolland, L. Thanh, J. Laloe, J. Huang, L. Edge, H. M. Wang, M. Gribelyuk, D. Rath, R. Bingert, Y. Liu, R. Bao, I. Kim, R. Ramachandran, W. Lai, J. Cutler, D. S. Salvador, Y. Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R. Divakaruni, X. Chen, M. Chudzik","doi":"10.1109/VLSIT.2012.6242445","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242445","url":null,"abstract":"Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121708996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Comprehensive investigations on neutral and attractive traps in random telegraph signal noise phenomena using (100)- and (110)-orientated CMOSFETs 利用(100)和(110)定向cmosfet对随机电报信号噪声现象中的中性陷阱和吸引陷阱进行综合研究
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242501
J. Chen, I. Hirano, K. Tatsumura, Y. Mitani
{"title":"Comprehensive investigations on neutral and attractive traps in random telegraph signal noise phenomena using (100)- and (110)-orientated CMOSFETs","authors":"J. Chen, I. Hirano, K. Tatsumura, Y. Mitani","doi":"10.1109/VLSIT.2012.6242501","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242501","url":null,"abstract":"Neutral traps and attractive traps in random telegraph noise (RTN), on both (100)- and (110)-orientated CMOSFETs, are well distinguished and systematically studied for the first time, including both electron and hole traps. It is found that neutral traps energy distributions are higher than attractive traps and, most importantly, neutral traps caused much larger threshold voltage shifts (ΔVth_RTN) than attractive traps do, especially in (110)-nMOSFETs. Furthermore, based on obtained ΔVth_RTN in CMOSFETs on surface of various orientations, 3D structure optimizations are discussed in view of ΔVth_RTN suppression.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127886124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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