U. Kwon, K. Wong, S. Krishnan, L. Econimikos, X. Zhang, C. Ortolland, L. Thanh, J. Laloe, J. Huang, L. Edge, H. M. Wang, M. Gribelyuk, D. Rath, R. Bingert, Y. Liu, R. Bao, I. Kim, R. Ramachandran, W. Lai, J. Cutler, D. S. Salvador, Y. Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R. Divakaruni, X. Chen, M. Chudzik
{"title":"一种新颖的低阻栅极填充物,用于20nm及以上栅极长度缩放,用于栅极末高k/金属栅极CMOS技术","authors":"U. Kwon, K. Wong, S. Krishnan, L. Econimikos, X. Zhang, C. Ortolland, L. Thanh, J. Laloe, J. Huang, L. Edge, H. M. Wang, M. Gribelyuk, D. Rath, R. Bingert, Y. Liu, R. Bao, I. Kim, R. Ramachandran, W. Lai, J. Cutler, D. S. Salvador, Y. Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R. Divakaruni, X. Chen, M. Chudzik","doi":"10.1109/VLSIT.2012.6242445","DOIUrl":null,"url":null,"abstract":"Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology\",\"authors\":\"U. Kwon, K. Wong, S. Krishnan, L. Econimikos, X. Zhang, C. Ortolland, L. Thanh, J. Laloe, J. Huang, L. Edge, H. M. Wang, M. Gribelyuk, D. Rath, R. Bingert, Y. Liu, R. Bao, I. Kim, R. Ramachandran, W. Lai, J. Cutler, D. S. Salvador, Y. Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R. Divakaruni, X. Chen, M. Chudzik\",\"doi\":\"10.1109/VLSIT.2012.6242445\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.\",\"PeriodicalId\":266298,\"journal\":{\"name\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2012.6242445\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242445","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.