{"title":"采用III-V纳米线/硅异质结的陡坡隧道场效应晶体管","authors":"K. Tomioka, M. Yoshimura, T. Fukui","doi":"10.1109/VLSIT.2012.6242454","DOIUrl":null,"url":null,"abstract":"In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"151","resultStr":"{\"title\":\"Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction\",\"authors\":\"K. Tomioka, M. Yoshimura, T. Fukui\",\"doi\":\"10.1109/VLSIT.2012.6242454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.\",\"PeriodicalId\":266298,\"journal\":{\"name\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"151\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2012.6242454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction
In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.