高纵横比通过硅通孔(TSV)技术

H. B. Chang, H. Y. Chen, P. Kuo, C. H. Chien, E. Liao, T. Lin, T. S. Wei, Y. Lin, Y. H. Chen, K. Yang, H. A. Teng, W. Tsai, Y. Tseng, S. Y. Chen, C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, S. Hou, W. Chiou, S. Jeng, C. H. Yu
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引用次数: 17

摘要

通过硅通孔(TSV)的密度受TSV尺寸和保持区(KOZ)的限制。在28nm CMOS基准上验证了2 μm × 30 μm的高纵横比Cu TSV工艺,具有良好的电学性能和较低的成本。通过施加2 μm × 30 μm的TSV,可以消除TSV附近因热膨胀引起的Si应力。因此,TSV应力的松弛与最小保持区(KOZ)有关。优异的3D-IC良率和高宽高比TSV嵌入式器件特性的实现是硅代工技术实现3D-IC可制造性的关键里程碑。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High-aspect ratio through silicon via (TSV) technology
The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.
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