由一种新型自对准独立控制双栅串选择晶体管(SSL)解码的高间距可伸缩3D垂直栅(VG) NAND闪存

Chih-Ping Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Shih-Hung Chen, Y. Shih, K. Hsieh, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
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引用次数: 19

摘要

除了垂直堆叠外,3D NAND闪存的横向缩放至关重要,否则需要> 16层堆叠层才能与20nm 2D NAND具有成本竞争力。在这项工作中,我们提出了一种3D垂直栅(VG) NAND,使用自对准独立控制双栅(IDG)串选择晶体管(SSL)解码方法。IDG SSL提供了出色的程序抑制和读取选择,而不会影响单元尺寸的增加,使我们的3D VG NAND单元具有传统2D NAND的可扩展性。我们呈现了世界上第一个<;50nm (37.5nm)半间距3D NAND。详细说明了BL解码和页面操作方法。这种具有IDG SSL方法的高间距可扩展VG提供了非常具有成本竞争力的3D NAND。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
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