发布求助
文献互助 智能选刊 最新文献

2012 Symposium on VLSI Technology (VLSIT)最新文献

筛选
英文 中文
A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell 32nm高k和金属栅防熔丝阵列，具有1.01µm2 1T1C位单元
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242470
S. Kulkarni, S. Pae, Zhanping Chen, W. Hafez, B. Pedersen, A. Rahman, T. Tong, U. Bhattacharya, C. Jan, K. Zhang
{"title":"A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell","authors":"S. Kulkarni, S. Pae, Zhanping Chen, W. Hafez, B. Pedersen, A. Rahman, T. Tong, U. Bhattacharya, C. Jan, K. Zhang","doi":"10.1109/VLSIT.2012.6242470","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242470","url":null,"abstract":"A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications 先进的建模和优化高性能32nm HKMG SOI CMOS射频/模拟SoC应用
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242498
S. Lee, J. Johnson, B. Greene, A. Chou, K. Zhao, M. Chowdhury, J. Sim, A. Kumar, D. Kim, A. Sutton, S. Ku, Y. Liang, Y. Wang, D. Slisher, K. Duncan, P. Hyde, R. Thoma, J. Deng, Y. Deng, R. Rupani, R. Williams, L. Wagner, C. Wermer, H. Li, B. Johnson, D. Daley, J. Plouchart, S. Narasimha, C. Putnam, E. Maciejewski, W. Henson, S. Springer
{"title":"Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications","authors":"S. Lee, J. Johnson, B. Greene, A. Chou, K. Zhao, M. Chowdhury, J. Sim, A. Kumar, D. Kim, A. Sutton, S. Ku, Y. Liang, Y. Wang, D. Slisher, K. Duncan, P. Hyde, R. Thoma, J. Deng, Y. Deng, R. Rupani, R. Williams, L. Wagner, C. Wermer, H. Li, B. Johnson, D. Daley, J. Plouchart, S. Narasimha, C. Putnam, E. Maciejewski, W. Henson, S. Springer","doi":"10.1109/VLSIT.2012.6242498","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242498","url":null,"abstract":"We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging device modeling features and their enhancements. At nominal Lpoly, floating-body NFET and PFET demonstrate peak fT of 300GHz and fMAX of higher than 350GHz with excellent model-to-hardware accuracy. For precision analog circuit design, body-contacted (BC) FETs and various passives are offered, and their performance and modeling accuracy are co-optimized to push the technology limit and achieve state-of-the-art circuits, e.g., 28Gb/s serial link transceiver and LC-tank VCO operating at higher than 100GHz.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation 专为超低电压薄盒上硅(SOTB) CMOS工作的Poly/high-k/SiON栅极堆栈和新型轮廓工程
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242485
Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto
{"title":"Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation","authors":"Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto","doi":"10.1109/VLSIT.2012.6242485","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242485","url":null,"abstract":"We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115963664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length 平面FDSOI和p型mosfet中机械应力源的效率降至14nm栅极长度
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242486
S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J. Hartmann, J. Barbe, J. Mazurier, P. Nguyen, C. Fenouillet-Béranger, C. Tabone, L. Tosti, L. Brevard, A. Toffoli, F. Allain, D. Lafond, B. Nguyen, G. Ghibaudo, F. Boeuf, O. Faynot, T. Poiroux
{"title":"Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length","authors":"S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J. Hartmann, J. Barbe, J. Mazurier, P. Nguyen, C. Fenouillet-Béranger, C. Tabone, L. Tosti, L. Brevard, A. Toffoli, F. Allain, D. Lafond, B. Nguyen, G. Ghibaudo, F. Boeuf, O. Faynot, T. Poiroux","doi":"10.1109/VLSIT.2012.6242486","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242486","url":null,"abstract":"We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I<sub>ON,n</sub>/I<sub>ON,p</sub>=1148/1014μA/μm drive current at I<sub>OFF,n</sub>/I<sub>OFF,p</sub>=55/16nA/μm leakage current (V<sub>DD</sub>=1V) with excellent V<sub>T</sub>-matching (A<sub>VT</sub> <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I<sub>ON,n</sub> up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126633954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax InAs量子阱MOSFET (Lg = 100 nm)具有创纪录的高gm, fT和fmax
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242520
T. Kim, R. Hill, C. Young, D. Veksler, L. Morassi, S. Oktybrshky, J. Oh, C. Kang, D. Kim, J. D. del Alamo, C. Hobbs, P. Kirsch, R. Jammy
{"title":"InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax","authors":"T. Kim, R. Hill, C. Young, D. Veksler, L. Morassi, S. Oktybrshky, J. Oh, C. Kang, D. Kim, J. D. del Alamo, C. Hobbs, P. Kirsch, R. Jammy","doi":"10.1109/VLSIT.2012.6242520","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242520","url":null,"abstract":"This paper reports InAs quantum-well (QW) MOSFETs with record transconductance (g<sub>m,max</sub> = 1.73 mS/μm) and high-frequency performance (f<sub>T</sub> = 245 GHz and f<sub>max</sub> = 355 GHz) at L<sub>g</sub> = 100 nm. This record performance is achieved by using a low D<sub>it</sub> composite Al<sub>2</sub>O<sub>3</sub>/InP gate stack, optimized layer design and a high mobility InAs channel. This work is significant because it shows a possible III-V material pathway from In<sub>1-x</sub>Ga<sub>x</sub>As to InAs with similar processing and generalized characterization, including D<sub>it</sub>.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
High performance bilayer oxide transistor for gate driver circuitry implemented on power electronic devices 用于电力电子器件栅极驱动电路的高性能双层氧化物晶体管
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242493
S. Jeon, Hojung Kim, Hyunsik Choi, I. Song, Seung‐Eon Ahn, C. J. Kim, Jaikwang Shin, U. Chung, I. Yoo, Kinam Kim
{"title":"High performance bilayer oxide transistor for gate driver circuitry implemented on power electronic devices","authors":"S. Jeon, Hojung Kim, Hyunsik Choi, I. Song, Seung‐Eon Ahn, C. J. Kim, Jaikwang Shin, U. Chung, I. Yoo, Kinam Kim","doi":"10.1109/VLSIT.2012.6242493","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242493","url":null,"abstract":"The integration of electronically active oxide transistors onto silicon circuits represents an innovative approach to improving the performance of devices. In this paper, we present high performance oxide transistor for use as gate drive circuitry integrated on top of a power electronic device, providing a novel power system. Specifically, as a core device component in gate driver, oxide transistor exhibits remarkable performance such as, high mobility (23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process temperatures (<;300°C). In addition, we demonstrate the dynamic behavior of the inverter and the latch produced by oxide transistor and thus a complete and functioning gate drive circuitry can be implemented on top of power management integrated circuit (PMIC) as depicted in the report.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results 通过原子模拟和实验结果的桥接，了解缩放III-V型TFET用于逻辑的可行性
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242522
U. Avci, S. Hasan, D. Nikonov, R. Rios, K. Kuhn, I. Young
{"title":"Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results","authors":"U. Avci, S. Hasan, D. Nikonov, R. Rios, K. Kuhn, I. Young","doi":"10.1109/VLSIT.2012.6242522","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242522","url":null,"abstract":"A detailed comparison between III-V TFET's experimental characteristics and atomistic quantum mechanical predictions is reported to study the validity of the performance improvement predictions of a scaled TFET. Simulations did not employ any fitting parameters to match the experimental data, but instead used material and geometry parameters as the only inputs. The results show that the experimental and simulation characteristics are in reasonable agreement, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability. The differences between scaled TFET predictions and large experimental TFET devices are shown to be due to the geometry, meaning that improved electrostatics with thin body and double-gate (DG) is required for TFET scaling. Results demonstrate that the III-V TFET is a realistic candidate for future low-voltage logic applications.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127632923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM) 基于片上SPRAM(自旋传递扭矩RAM)的3d堆叠可重构自旋逻辑芯片的超快并行重构
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242515
T. Tanaka, H. Kino, R. Nakazawa, K. Kiyoyama, H. Ohno, M. Koyanagi
{"title":"Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)","authors":"T. Tanaka, H. Kino, R. Nakazawa, K. Kiyoyama, H. Ohno, M. Koyanagi","doi":"10.1109/VLSIT.2012.6242515","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242515","url":null,"abstract":"We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"545 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Conductive filament scaling of TaOx bipolar ReRAM for long retention with low current operation TaOx双极ReRAM的导电丝标度在低电流操作下长时间保持
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242467
T. Ninomiya, T. Takagi, Z. Wei, S. Muraoka, R. Yasuhara, K. Katayama, Y. Ikeda, K. Kawai, Y. Kato, Y. Kawashima, S. Ito, T. Mikawa, K. Shimakawa, K. Aono
{"title":"Conductive filament scaling of TaOx bipolar ReRAM for long retention with low current operation","authors":"T. Ninomiya, T. Takagi, Z. Wei, S. Muraoka, R. Yasuhara, K. Katayama, Y. Ikeda, K. Kawai, Y. Kato, Y. Kawashima, S. Ito, T. Mikawa, K. Shimakawa, K. Aono","doi":"10.1109/VLSIT.2012.6242467","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242467","url":null,"abstract":"We demonstrate for the first time that the density of oxygen vacancy in a conductive filament plays a key role in ensuring data retention. We achieve very good retention results up to 100 hours at 150°C even under the low current operation due to the scaling of conductive filament size while retaining sufficiently high density of oxygen vacancy.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114421113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Recent progress and challenges for relay logic switch technology 继电器逻辑开关技术的最新进展与挑战
2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI: 10.1109/VLSIT.2012.6242452
T. Liu, L. Hutin, I. Chen, R. Nathanael, Yenhao Chen, M. Spencer, E. Alon
{"title":"Recent progress and challenges for relay logic switch technology","authors":"T. Liu, L. Hutin, I. Chen, R. Nathanael, Yenhao Chen, M. Spencer, E. Alon","doi":"10.1109/VLSIT.2012.6242452","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242452","url":null,"abstract":"The energy efficiency of CMOS technology is fundamentally limited by transistor off-state leakage (IOFF). Mechanical switches have zero IOFF and therefore could be advantageous for ultra-low-power digital logic applications. This paper discusses recent advancements in relay logic switch technology and current challenges which must be addressed to realize its promise.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125597621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信