平面FDSOI和p型mosfet中机械应力源的效率降至14nm栅极长度

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242486

S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J. Hartmann, J. Barbe, J. Mazurier, P. Nguyen, C. Fenouillet-Béranger, C. Tabone, L. Tosti, L. Brevard, A. Toffoli, F. Allain, D. Lafond, B. Nguyen, G. Ghibaudo, F. Boeuf, O. Faynot, T. Poiroux

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引用次数: 16

摘要

我们制备的高应力完全耗尽绝缘体上硅(FDSOI) n和pmosfet在IOFF时达到ION,n/ION,p=1148/1014μA/μm驱动电流，n/IOFF,p=55/16nA/μm泄漏电流(VDD=1V)，具有良好的vt匹配(AVT ON,n高达22%)，并降低了pmosfet的SiGe源和漏极效率。然而，0°(;)取向仍然是高应力pmosfet的最佳配置，并为CMOS提供了最佳折衷。

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Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I_ON,n/I_ON,p=1148/1014μA/μm drive current at I_OFF,n/I_OFF,p=55/16nA/μm leakage current (V_DD=1V) with excellent V_T-matching (A_VT <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I_ON,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.

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2012 Symposium on VLSI Technology (VLSIT)

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