Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

Abstract

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.