专为超低电压薄盒上硅(SOTB) CMOS工作的Poly/high-k/SiON栅极堆栈和新型轮廓工程

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242485

Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto

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引用次数: 17

摘要

我们首次展示了专为低至0.4 V的超低电压(ULV)工作而设计的薄埋氧化硅(SOTB) CMOS。利用i)具有高k的双多栅极堆栈，具有最适合ULV CMOS操作的四分之一间隙工作功能，以及ii)一种新的“局部地平面(LGP)”结构，该结构显着改善了短通道效应(第v次滚出)，而不会增加局部可变性，与体晕不同，采用自适应体偏置(ABB)方案证明了低泄漏SRAM操作。

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Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.

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2012 Symposium on VLSI Technology (VLSIT)

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