{"title":"Wearable sensing systems for healthcare monitoring","authors":"I. Yamada, G. Lopez","doi":"10.1109/VLSIT.2012.6242435","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242435","url":null,"abstract":"Since our society is rapidly aging, there exists an urgent need to shift from passive medical care to preventive medicine and health management, to improve individuals' quality of life and reduce medical expenses. At the same time, rapid advances in micro-machine and LSI technologies with revolutionary advances in wireless information and communication technology have enabled development of wearable sensing systems for healthcare monitoring in daily life. We have been developing a comprehensive physiological and environmental information processing platform on the basis of wearable sensors for services to counter lifestyle diseases. This paper focuses on wearable physiological sensing and its applications to healthcare.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125603445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi
{"title":"Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture","authors":"Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi","doi":"10.1109/VLSIT.2012.6242462","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242462","url":null,"abstract":"A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ~6 (Perror)2 when the error rate per DWM cell was Perror. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128128473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Degraeve, A. Fantini, S. Clima, B. Govoreanu, L. Goux, Yangyin Chen, D. Wouters, P. Roussel, G. Kar, G. Pourtois, S. Cosemans, J. Kittl, G. Groeseneken, M. Jurczak, L. Altimime
{"title":"Dynamic ‘hour glass’ model for SET and RESET in HfO2 RRAM","authors":"R. Degraeve, A. Fantini, S. Clima, B. Govoreanu, L. Goux, Yangyin Chen, D. Wouters, P. Roussel, G. Kar, G. Pourtois, S. Cosemans, J. Kittl, G. Groeseneken, M. Jurczak, L. Altimime","doi":"10.1109/VLSIT.2012.6242468","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242468","url":null,"abstract":"An analytic dynamic hour glass model for HfO2 RRAM is demonstrated, describing the reset as a dynamic equilibrium process and the set as a constriction growth limited by ion mobility and current compliance. The dependence on time, voltage and forming conditions is in good constriction growth agreement with experiments. Since the model is fully analytical, it can be implemented in a circuit simulator.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122763217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kaneko, H. Sunamura, M. Narihiro, S. Saito, N. Furutake, M. Hane, Y. Hayashi
{"title":"Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches","authors":"K. Kaneko, H. Sunamura, M. Narihiro, S. Saito, N. Furutake, M. Hane, Y. Hayashi","doi":"10.1109/VLSIT.2012.6242492","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242492","url":null,"abstract":"Functional circuit elements based on novel BEOL-transistors with a wide-band-gap oxide semiconductor InGaZnO (IGZO) film are integrated onto LSI Cu-interconnects, and their operations are demonstrated. High-current comb-type transistors show excellent Ion/Ioff ratio (>;108) and high-Vd operation with linear area dependence, realizing area-saving compact high-current BEOL switches. Successful operation of voltage-controlled inverter switches with high-Vd enables on-chip bridging I/Os between high/low voltage on conventional Si system LSIs. Setting the gate-to-drain offset design to just 0.1μm realizes +20V enhancement of the breakdown voltage to ~60V with excellent safety operation at around Vd=50V due to the wide-band-gap characteristics.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"60 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Yu, Jie Deng, Sim Loo, K. Dezfulian, S. Lichtensteiger, J. Bickford, N. Habib, P. Chang, A. Mocuta, K. Rim
{"title":"Accurate chip leakage prediction: Challenges and solutions","authors":"X. Yu, Jie Deng, Sim Loo, K. Dezfulian, S. Lichtensteiger, J. Bickford, N. Habib, P. Chang, A. Mocuta, K. Rim","doi":"10.1109/VLSIT.2012.6242526","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242526","url":null,"abstract":"A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134448365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, N. Mukherjee, M. Radosavljevic
{"title":"III–V field effect transistors for future ultra-low power applications","authors":"G. Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, N. Mukherjee, M. Radosavljevic","doi":"10.1109/VLSIT.2012.6242453","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242453","url":null,"abstract":"This paper summarizes the electrostatics and performance of III-V field effect transistors including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs (TFETs). The electrostatics of the III-V devices is shown to improve from thick body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET structures, sub-threshold slope (SS) steeper than 60 mV/decade has been demonstrated in III-V TFETs. These III-V devices, especially the 3-D tri-gate MOSFET and TFET, are viable options for future ultra low power applications.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wootae Lee, Jubong Park, Jungho Shin, J. Woo, Seonghyun Kim, G. Choi, Seungjae Jung, Sangsu Park, Daeseok Lee, E. Cha, H. Lee, S. Kim, Suock Chung, H. Hwang
{"title":"Varistor-type bidirectional switch (JMAX>107A/cm2, selectivity∼104) for 3D bipolar resistive memory arrays","authors":"Wootae Lee, Jubong Park, Jungho Shin, J. Woo, Seonghyun Kim, G. Choi, Seungjae Jung, Sangsu Park, Daeseok Lee, E. Cha, H. Lee, S. Kim, Suock Chung, H. Hwang","doi":"10.1109/VLSIT.2012.6242449","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242449","url":null,"abstract":"We demonstrate a varistor-type bidirectional switch (VBS) with excellent selection property for future 3D bipolar resistive memory array. A highly non-linear VBS showed superior performances including high current density (>;3×10<sup>7</sup>A/cm<sup>2</sup>) and high selectivity (~10<sup>4</sup>). The non-linear I-V characteristics can be explained by varistor-type multi-layer tunnel barriers, which were formed by Ta incorporation into thin TiO<sub>2</sub>. Furthermore, the 1S1R device showed excellent suppression of leakage current (>;10<sup>4</sup> reduction) at 1/2V<sub>READ</sub>, which is promising for ultra-high density resistive memory applications.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Chiou, K. Yang, J. L. Yeh, S. H. Wang, Y. Liou, T. J. Wu, J. Lin, C. Huang, S. W. Lu, C. Hsieh, H. A. Teng, C. Chiu, H. B. Chang, T. S. Wei, Y. Lin, Y. H. Chen, H. Tu, H. Ko, T. Yu, J. Hung, P. Tsai, D. Yeh, W. Wu, A. Su, S. Chiu, S. Hou, D. Shih, K. H. Chen, S. Jeng, C. H. Yu
{"title":"An ultra-thin interposer utilizing 3D TSV technology","authors":"W. Chiou, K. Yang, J. L. Yeh, S. H. Wang, Y. Liou, T. J. Wu, J. Lin, C. Huang, S. W. Lu, C. Hsieh, H. A. Teng, C. Chiu, H. B. Chang, T. S. Wei, Y. Lin, Y. H. Chen, H. Tu, H. Ko, T. Yu, J. Hung, P. Tsai, D. Yeh, W. Wu, A. Su, S. Chiu, S. Hou, D. Shih, K. H. Chen, S. Jeng, C. H. Yu","doi":"10.1109/VLSIT.2012.6242484","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242484","url":null,"abstract":"To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116275898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, Derek K. Jones, J. Jopling, S. Joshi, C. Kenyon, Huichu Liu, R. McFadden, B. Mcintyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. PradhanSameer, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry
{"title":"A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors","authors":"C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, Derek K. Jones, J. Jopling, S. Joshi, C. Kenyon, Huichu Liu, R. McFadden, B. Mcintyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. PradhanSameer, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry","doi":"10.1109/VLSIT.2012.6242496","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242496","url":null,"abstract":"A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70mV/dec) and very low DIBL (~50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sungchul Lee, Kwang-suk Kim, K. Kim, U. Pi, Y. Jang, U. Chung, I. Yoo, Kinam Kim
{"title":"Highly scalable STT-MRAM with 3-dimensional cell structure using in-plane magnetic anisotropy materials","authors":"Sungchul Lee, Kwang-suk Kim, K. Kim, U. Pi, Y. Jang, U. Chung, I. Yoo, Kinam Kim","doi":"10.1109/VLSIT.2012.6242463","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242463","url":null,"abstract":"Novel spin transfer torque MRAM cells with three dimensional freelayer structures were suggested for the high density memory below 20nm technology node. By folding the freelayer to a special geometry, the 3D MTJ Cell structure retains large freelayer volume without an increase of cell foot-print, scaling down the MRAM cells even with in-plane magnetic anisotropy materials. From the micromagnetic calculation with Nudged Elastic Band (NEB) method, we confirmed the thermal stability over 60 in 3D MTJ cell with 15×30 nm2 area.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133018761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
