A. K. Kambham, G. Zschaetzsch, Y. Sasaki, M. Togo, N. Horiguchi, J. Mody, A. Florakis, D. Gajula, A. Kumar, M. Gilbert, W. Vandervorst
{"title":"Atom Probe Tomography for 3D-dopant analysis in FinFET devices","authors":"A. K. Kambham, G. Zschaetzsch, Y. Sasaki, M. Togo, N. Horiguchi, J. Mody, A. Florakis, D. Gajula, A. Kumar, M. Gilbert, W. Vandervorst","doi":"10.1109/VLSIT.2012.6242469","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242469","url":null,"abstract":"As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate methodology this is feasible using Atom Probe Tomography (APT). We extract the 3D-dopant profile and important parameters such as gate overlap and profile steepness, from transistor formed with plasma doping processes. Analyzing samples with different doping processes, the APT results are entirely consistent with device performances (Ioff vs. Ion).","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Veloso, Y. Higuchi, S. Chew, K. Devriendt, L. Ragnarsson, F. Sebaai, T. Schram, S. Brus, E. Vecchio, K. Kellens, E. Rohr, G. Eneman, E. Simoen, M. Cho, V. Paraschiv, Y. Crabbe, X. Shi, H. Tielens, A. Van Ammel, H. Dekkers, P. Favia, J. Geypen, H. Bender, A. Phatak, J. I. del Agua Borniquel, K. Xu, M. Allen, C. Liu, T. Xu, W. Yoo, A. Thean, N. Horiguchi
{"title":"Process control & integration options of RMG technology for aggressively scaled devices","authors":"A. Veloso, Y. Higuchi, S. Chew, K. Devriendt, L. Ragnarsson, F. Sebaai, T. Schram, S. Brus, E. Vecchio, K. Kellens, E. Rohr, G. Eneman, E. Simoen, M. Cho, V. Paraschiv, Y. Crabbe, X. Shi, H. Tielens, A. Van Ammel, H. Dekkers, P. Favia, J. Geypen, H. Bender, A. Phatak, J. I. del Agua Borniquel, K. Xu, M. Allen, C. Liu, T. Xu, W. Yoo, A. Thean, N. Horiguchi","doi":"10.1109/VLSIT.2012.6242447","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242447","url":null,"abstract":"We report on aggressively scaled RMG-HKL devices, with tight low-V<sub>T</sub> distributions [σ(V<sub>Tsat</sub>) ~ 29mV (PMOS), ~ 49mV (NMOS) at L<sub>gate</sub>~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H<sub>gate</sub>, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R<sub>gate</sub> distributions down to L<sub>gate</sub>~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H<sub>gate</sub>~60nm, L<sub>gate</sub>≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO<sub>2</sub> post-deposition N<sub>2</sub>-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125491468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SRAM design in nano-scale CMOS technologies (Invited)","authors":"Kevin Zhang, E. Karl, Yih Wang","doi":"10.1109/VLSIT.2012.6242473","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242473","url":null,"abstract":"SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to follow Moore's law well into the future.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123962880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ikeda, M. Ono, D. Kosemura, K. Usuda, M. Oda, Y. Kamimuta, T. Irisawa, Y. Moriyama, A. Ogura, T. Tezuka
{"title":"High-mobility and low-parasitic resistance characteristics in strained Ge nanowire pMOSFETs with metal source/drain structure formed by doping-free processes","authors":"K. Ikeda, M. Ono, D. Kosemura, K. Usuda, M. Oda, Y. Kamimuta, T. Irisawa, Y. Moriyama, A. Ogura, T. Tezuka","doi":"10.1109/VLSIT.2012.6242513","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242513","url":null,"abstract":"Metal source/drain (S/D) Ge nanowire MOSFETs with a compressive strain as high as 3.8% were fabricated by the 2-step Ge-condensation technique without intentional doping for the S/D. Record high inversion hole mobility (μ<sub>eff</sub> = 855 cm<sup>2</sup>/Vs @ N<sub>s</sub> = 5×10<sup>12</sup>cm<sup>-2</sup>) and saturation drain current 731μA/μm at V<sub>d</sub>=-1V were achieved among Ge nanowire pFETs ever reported. It is found that the extremely low contact resistivity ρ<sub>c</sub> ~ 4×10<sup>-8</sup>O cm<sup>2</sup> for the Schottky contact contributes to the high saturation current as well as the high mobility.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129962211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson
{"title":"High performance bulk planar 20nm CMOS technology for low power mobile applications","authors":"H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson","doi":"10.1109/VLSIT.2012.6242495","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242495","url":null,"abstract":"In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Lee, Y. Y. Lin, M. Lee, W. Chien, H. Lung, K. Hsieh, C. Y. Lu
{"title":"A novel cross point one-resistor (0T1R) conductive bridge random access memory (CBRAM) with ultra low set/reset operation current","authors":"F. Lee, Y. Y. Lin, M. Lee, W. Chien, H. Lung, K. Hsieh, C. Y. Lu","doi":"10.1109/VLSIT.2012.6242464","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242464","url":null,"abstract":"Using the dual Vth characteristics of a multi-layer SiO2/SiO2/Cu-GST conducting bridge (CB) structure we can construct a one-resistor cell without an access device (0T1R). Like 1T Flash memory the Vth is used to store the logic state thus leaving all devices always at high resistance state and a separate isolation device is not needed. The Vth of the cell is determined by the presence of CB in the SiO2 layer only. The CB in the SiO2 is present only temporarily during reading, and is spontaneously dissolved afterward. This spontaneous rupture of the filament in the SiO2 layer greatly reduces the switching current as well as reducing the read disturb. The mechanism for the spontaneous rupture phenomenon is investigated.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131987373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Goux, A. Fantini, G. Kar, Y. Chen, N. Jossart, R. Degraeve, S. Clima, B. Govoreanu, G. Lorenzo, G. Pourtois, D. Wouters, J. Kittl, L. Altimime, M. Jurczak
{"title":"Ultralow sub-500nA operating current high-performance TiNAl2O3HfO2HfTiN bipolar RRAM achieved through understanding-based stack-engineering","authors":"L. Goux, A. Fantini, G. Kar, Y. Chen, N. Jossart, R. Degraeve, S. Clima, B. Govoreanu, G. Lorenzo, G. Pourtois, D. Wouters, J. Kittl, L. Altimime, M. Jurczak","doi":"10.1109/VLSIT.2012.6242510","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242510","url":null,"abstract":"We demonstrate sub-500nA switching and tunable set voltage by inserting thin Al2O3 layer in TiNHfO2HfTiN RRAM cell. Stack engineering clearly led to novel insights into the switching phenomenology: (i) O-scavenging is key in the forming process and stack-asymmetry management; (ii) dielectric-stack thinning allows lower forming current; (iii) `natural' (asymmetry-induced) reset switching takes place close to the TiN anode; (iv) reset resistance is limited by material-barrier properties at TiN interface.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128353513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dramatic improvement of high-k gate dielectric reliability by using mono-layer graphene gate electrode","authors":"Jong Kyung Park, S. Song, J. Mun, B. Cho","doi":"10.1109/VLSIT.2012.6242446","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242446","url":null,"abstract":"We demonstrate for the first time that the high-k gate dielectric reliability is dramatically improved by replacing metal gate electrode with graphene gate electrode. The atomic-scale thickness and flexible nature of graphene completely eliminate mechanical stress in the high-k gate dielectric, resulting in significant reduction of trap generation in the high-k film. Almost all the electrical properties related to reliability of MOSFET such as the PBTI, TDDB, leakage current, etc are significantly improved. Data retention and program/erase properties of charge trap Flash memory are also greatly improved.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Tsai, E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang
{"title":"The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique","authors":"H. Tsai, E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang","doi":"10.1109/VLSIT.2012.6242525","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242525","url":null,"abstract":"Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or NBTI-stress, induce the Vth variations. To identify these traps, for the first time, a unique random trap profiling feasible for 3D device applications has been demonstrated on trigate devices. For such devices, the oxide traps are generated not only near the drain side but also on the sidewall, after hot carrier (HC) and NBTI stresses. More importantly, the Vth variation in pMOSFET under NBTI becomes much worse as a result of an additional surface roughness effect. This method provides us a valuable tool for the diagnosis of reliability in 3D devices (e.g., FinFET).","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115637175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Park, Wook-Ghee Hahn, Ki-Whan Song, Kiwhan Choi, H. Choi, S. Lee, Changsub Lee, J. Song, Jin-Man Han, Kye Hyun Kyoung, Young-Hyun Jun
{"title":"A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices","authors":"I. Park, Wook-Ghee Hahn, Ki-Whan Song, Kiwhan Choi, H. Choi, S. Lee, Changsub Lee, J. Song, Jin-Man Han, Kye Hyun Kyoung, Young-Hyun Jun","doi":"10.1109/VLSIT.2012.6242442","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242442","url":null,"abstract":"We present a new field effect mechanism on IGIDL in NAND flash strings. According to the proposed 5-terminal GIDL model, special care should be taken to optimize the biasing levels of inhibit scheme. Suggested incremental biasing scheme can be one of the solutions for reducing critical field that enhances boosting efficiency and maximizes memory yields.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122468863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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