C. Fenouillet-Béranger, P. Perreau, O. Weber, I. Ben-Akkez, A. Cros, A. Bajolet, S. Haendler, P. Fonteneau, P. Gouraud, E. Richard, F. Abbate, D. Barge, D. Pellissier-Tanon, B. Dumont, F. Andrieu, J. Passieux, R. Bon, V. Barral, D. Golanski, D. Petit, N. Planes, O. Bonin, W. Schwarzenbach, T. Poiroux, O. Faynot, M. Haond, F. Boeuf
{"title":"Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates","authors":"C. Fenouillet-Béranger, P. Perreau, O. Weber, I. Ben-Akkez, A. Cros, A. Bajolet, S. Haendler, P. Fonteneau, P. Gouraud, E. Richard, F. Abbate, D. Barge, D. Pellissier-Tanon, B. Dumont, F. Andrieu, J. Passieux, R. Bon, V. Barral, D. Golanski, D. Petit, N. Planes, O. Bonin, W. Schwarzenbach, T. Poiroux, O. Faynot, M. Haond, F. Boeuf","doi":"10.1109/VLSIT.2012.6242488","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242488","url":null,"abstract":"For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530μA/μm @ Ioff=100nA/μm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12μm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seonghyun Kim, Xinjun Liu, Jubong Park, Seungjae Jung, Wootae Lee, J. Woo, Jungho Shin, G. Choi, Chumhum Cho, Sangsu Park, Daeseok Lee, E. Cha, B. Lee, H. Lee, S. Kim, Suock Chung, H. Hwang
{"title":"Ultrathin (<10nm) Nb2O5/NbO2 hybrid memory with both memory and selector characteristics for high density 3D vertically stackable RRAM applications","authors":"Seonghyun Kim, Xinjun Liu, Jubong Park, Seungjae Jung, Wootae Lee, J. Woo, Jungho Shin, G. Choi, Chumhum Cho, Sangsu Park, Daeseok Lee, E. Cha, B. Lee, H. Lee, S. Kim, Suock Chung, H. Hwang","doi":"10.1109/VLSIT.2012.6242508","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242508","url":null,"abstract":"We report, for the first time, the novel concept of ultrathin (~10nm) W/NbO<sub>x</sub>/Pt device with both threshold switching (TS) and memory switching (MS) characteristics. Excellent TS characteristics of NbO<sub>2</sub>, such as high temperature stability (~160°C), fast switching speed (~22ns), good switching uniformity, and extreme scalability of device area (φ~10nm)/thickness (~10nm) were obtained. By oxidizing NbO<sub>2</sub>, we can form ultrathin Nb<sub>2</sub>O<sub>5</sub>/NbO<sub>2</sub> stack layer for hybrid memory devices with both TS and MS. Without additional selector device, 1Kb cross-point hybrid memory device without SET/RESET disturbance up to 10<sup>6</sup> cycles was demonstrated.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Ragnarsson, C. Adelmann, Y. Higuchi, K. Opsomer, A. Veloso, S. Chew, E. Rohr, E. Vecchio, Xiaoping Shi, K. Devriendt, F. Sebaai, T. Kauerauf, M. Pawlak, T. Schram, S. Van Elshocht, N. Horiguchi, A. Thean
{"title":"Implementing cubic-phase HfO2 with κ-value ∼ 30 in low-VT replacement gate pMOS devices for improved EOT-Scaling and reliability","authors":"L. Ragnarsson, C. Adelmann, Y. Higuchi, K. Opsomer, A. Veloso, S. Chew, E. Rohr, E. Vecchio, Xiaoping Shi, K. Devriendt, F. Sebaai, T. Kauerauf, M. Pawlak, T. Schram, S. Van Elshocht, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2012.6242444","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242444","url":null,"abstract":"Higher κ-value HfO<sub>2</sub> (κ~30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO<sub>2</sub> causing crystallization into the cubic phase. The resulting gate-stack has up to 10<sup>3</sup> × lower gate-leakage current compared to a reference HfO<sub>2</sub>: J<sub>G</sub> at -1 V ~ 2 μA/cm<sup>2</sup> at EOT~9.7 Å. The better J<sub>G</sub> - EOT-scaling, result in performance and reliability improvements when normalized to the J<sub>G</sub>.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127648701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tatsuya Ohguro, Yusuke Higashi, K. Okano, Satoshi Inaba, Yoshiaki Toyoshima
{"title":"The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET","authors":"Tatsuya Ohguro, Yusuke Higashi, K. Okano, Satoshi Inaba, Yoshiaki Toyoshima","doi":"10.1109/VLSIT.2012.6242505","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242505","url":null,"abstract":"In planar MOSFET, the optimization of finger length should be carried out with considering fT, fmax and flicker noise because the noise degradation at STI edge effect appears below 1μm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Gong, S. Su, B. Liu, Lanxiang Wang, W. Wang, Yue Yang, E. Kong, B. Cheng, G. Han, Y. Yeo
{"title":"Towards high performance Ge1−xSnx and In0.7Ga0.3As CMOS: A novel common gate stack featuring sub-400 °C Si2H6 passivation, single TaN metal gate, and sub-1.3 nm EOT","authors":"X. Gong, S. Su, B. Liu, Lanxiang Wang, W. Wang, Yue Yang, E. Kong, B. Cheng, G. Han, Y. Yeo","doi":"10.1109/VLSIT.2012.6242480","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242480","url":null,"abstract":"We report a novel common gate stack solution for Ge<sub>1-x</sub>Sn<sub>x</sub> P-MOSFET and In<sub>0.7</sub>Ga<sub>0.3</sub>As N-MOSFET, featuring sub-400°C Si<sub>2</sub>H<sub>6</sub> passivation, sub-1.3 nm EOT, and single TaN metal gate. Symmetric V<sub>TH</sub>, high performance, low gate leakage, negligible hysteresis, and excellent reliability were realized. Using this gate stack, the world's first GeSn short-channel device with gate length L<sub>G</sub> down to 250 nm was realized. Drive current of more than 1000 μA/μm was achieved, with peak intrinsic transconductance of ~465 μS/μm at V<sub>DS</sub> of -1.1 V.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mitard, L. Witters, G. Eneman, G. Hellings, L. Pantisano, A. Hikavyy, R. Loo, P. Eyben, N. Horiguchi, A. Thean
{"title":"85nm-wide 1.5mA/µm-ION IFQW SiGe-pFET: Raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study","authors":"J. Mitard, L. Witters, G. Eneman, G. Hellings, L. Pantisano, A. Hikavyy, R. Loo, P. Eyben, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2012.6242512","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242512","url":null,"abstract":"Beside the V<sub>TH</sub>-tunability, a raised SiGe S/D module offers higher L<sub>G</sub>-scalability than an embedded SiGe S/D in SiGe-IFQW pFETs. In-depth transport study of record performing 1.5mA/μm-I<sub>ON</sub> strained-SiGe IFQW pFETs reveals that mobility improvement is still the key performance booster whereas L<sub>G</sub>-scaling has limited impact.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126918329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeong-heon Park, Y. Kim, W. C. Lim, J. H. Kim, S. H. Park, W. Kim, K. Kim, J. Jeong, K. S. Kim, H. Kim, Y. J. Lee, S. C. Oh, J. E. Lee, S. O. Park, S. Watts, D. Apalkov, V. Nikitin, M. Krounbi, S. Jeong, S. Choi, H. K. Kang, C. Chung
{"title":"Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy","authors":"Jeong-heon Park, Y. Kim, W. C. Lim, J. H. Kim, S. H. Park, W. Kim, K. Kim, J. Jeong, K. S. Kim, H. Kim, Y. J. Lee, S. C. Oh, J. E. Lee, S. O. Park, S. Watts, D. Apalkov, V. Nikitin, M. Krounbi, S. Jeong, S. Choi, H. K. Kang, C. Chung","doi":"10.1109/VLSIT.2012.6242459","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242459","url":null,"abstract":"We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (Δ) varies as a function of MTJ dimension, MTJs with dual interfaces show Δ over 60 at 20nm node, while MTJs of single interface show Δ around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/Δ), ~1/2 level of single interface MTJs.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133691252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Kenney, K. Ang, K. Matthews, M. Liehr, M. Minakais, J. Pater, M. Rodgers, V. Kaushik, S. Novak, S. Gausepohl, C. Hobbs, P. Kirsch, R. Jammy
{"title":"FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface","authors":"C. Kenney, K. Ang, K. Matthews, M. Liehr, M. Minakais, J. Pater, M. Rodgers, V. Kaushik, S. Novak, S. Gausepohl, C. Hobbs, P. Kirsch, R. Jammy","doi":"10.1109/VLSIT.2012.6242439","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242439","url":null,"abstract":"This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm-2 dose produced the best result with a 31% reduction of extrinsic resistance and a corresponding Ion increase of 19%. This optimum Sb implant is shown to reduce specific contact resistivity (ρc) below 10-8Ω-cm2 by decreasing the SBH and increasing the barrier steepness. Electrostatic control comparable to the reference device indicates no degradation in short channel effects for either Sb, Ge or As. This low ρc is promising to address key FinFET scaling issues associated with parasitic series resistance for the 14nm node and beyond.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132084088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Yuan, A. Nainani, A. Kumar, X. Guan, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat
{"title":"InGaSb: Single channel solution for realizing III–V CMOS","authors":"Z. Yuan, A. Nainani, A. Kumar, X. Guan, B. R. Bennett, J. B. Boos, M. Ancona, K. Saraswat","doi":"10.1109/VLSIT.2012.6242523","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242523","url":null,"abstract":"There has been an upsurge of interest in the possibility of a low-power, high-performance CMOS based on III-V materials. For such a technology to be realized, advances are needed in a number of areas including: (a) comparable high performance from n- and p-channel devices for complementary logic; (b) reducing the impact of Dit; and (c) overcoming low density of states (DOS) of electrons which could limit the NMOS ION. In this study, methods are investigated that deliver improvements in these three areas (Fig. 1). We chose to work on the 6.1-6.2Å lattice constant system with InGaSb as the channel material because of its advantages in terms of band engineering and high mobility/offsets for both electrons and holes [1-2]. Despite its larger lattice constant, antimonide's are also found to be potentially more suitable for hetero-integration [3]. We demonstrate electron/hole mobility >; 4000/900cm2/Vs can be achieved in a single channel material. For the first time in III-V systems, both n- and p-channel transistors with one single channel material show comparable high on-current.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130978009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Yoshida, Xinyu Fu, Kun Xu, Y. Lei, H. Yang, Shiyu Sun, Hao Chen, A. Darlak, R. Donohoe, C. Lazik, R. Jakkaraju, A. Noori, S. Hung, I. Peidous, Chorng-Ping Chang, A. Brand
{"title":"Replacement metal gate extendible to 11 nm technology","authors":"N. Yoshida, Xinyu Fu, Kun Xu, Y. Lei, H. Yang, Shiyu Sun, Hao Chen, A. Darlak, R. Donohoe, C. Lazik, R. Jakkaraju, A. Noori, S. Hung, I. Peidous, Chorng-Ping Chang, A. Brand","doi":"10.1109/VLSIT.2012.6242471","DOIUrl":"https://doi.org/10.1109/VLSIT.2012.6242471","url":null,"abstract":"This paper describes novel Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows advantages in threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. By demonstrating better VTH variability, superior conductivity and gap fill, Co-Al shows extendibility to the 11nm metal gate and beyond.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121287413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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