{"title":"基于纳米级CMOS技术的SRAM设计(特邀)","authors":"Kevin Zhang, E. Karl, Yih Wang","doi":"10.1109/VLSIT.2012.6242473","DOIUrl":null,"url":null,"abstract":"SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to follow Moore's law well into the future.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"SRAM design in nano-scale CMOS technologies (Invited)\",\"authors\":\"Kevin Zhang, E. Karl, Yih Wang\",\"doi\":\"10.1109/VLSIT.2012.6242473\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to follow Moore's law well into the future.\",\"PeriodicalId\":266298,\"journal\":{\"name\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Technology (VLSIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2012.6242473\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242473","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SRAM design in nano-scale CMOS technologies (Invited)
SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to follow Moore's law well into the future.