H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson
{"title":"用于低功耗移动应用的高性能体平面20nm CMOS技术","authors":"H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson","doi":"10.1109/VLSIT.2012.6242495","DOIUrl":null,"url":null,"abstract":"In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"High performance bulk planar 20nm CMOS technology for low power mobile applications\",\"authors\":\"H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson\",\"doi\":\"10.1109/VLSIT.2012.6242495\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. 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High performance bulk planar 20nm CMOS technology for low power mobile applications
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.
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