利用3D TSV技术的超薄中间层

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242484

W. Chiou, K. Yang, J. L. Yeh, S. H. Wang, Y. Liou, T. J. Wu, J. Lin, C. Huang, S. W. Lu, C. Hsieh, H. A. Teng, C. Chiu, H. B. Chang, T. S. Wei, Y. Lin, Y. H. Chen, H. Tu, H. Ko, T. Yu, J. Hung, P. Tsai, D. Yeh, W. Wu, A. Su, S. Chiu, S. Hou, D. Shih, K. H. Chen, S. Jeng, C. H. Yu

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引用次数: 9

摘要

为了实现超小型封装解决方案，开发了一种利用透硅通孔(TSV)技术的超薄(50μm)硅中间层。在超薄中间层上堆叠薄芯片(200 μm)已经克服了处理薄晶圆和保持封装共面性的挑战。本文着重介绍了这种新型薄中间体的优点和改进的电性能。通过仿真和实验研究了硅层的翘曲行为，保证了硅层的可靠性和鲁棒性。通过在超薄中间层上堆叠薄模具，实现了封装厚度的减小，从而实现了高功能、小外形、更好的电气性能和强大的可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An ultra-thin interposer utilizing 3D TSV technology

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

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2012 Symposium on VLSI Technology (VLSIT)

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