28nm FDSOI技术平台，适用于高速低压数字应用

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242497

N. Planes, Olivier Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. Sassoulas, Xavier Federspiel, Antoine Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, David Petit, D. Golanski, C. Fenouillet-Béranger, N. Guillot, M. Rafik, Vincent Huard, S. Puget, X. Montagner, M. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, Michel Haond

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引用次数: 401

摘要

首次提出了采用FDSOI技术的完整平台。这项工作表明，在1.0V和0.6V下，速度分别提高了32%和84%，而与标准批量技术相比，没有增加工艺复杂性。我们将展示如何通过保持竞争泄漏值来显著减少内存访问时间，这要归功于高Iread。演示了~14Mb SRAM单元的产量，允许首次测量SRAM阵列的Vmin。

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28nm FDSOI technology platform for high-speed low-voltage digital applications

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

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2012 Symposium on VLSI Technology (VLSIT)

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