N. Planes, Olivier Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. Sassoulas, Xavier Federspiel, Antoine Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, David Petit, D. Golanski, C. Fenouillet-Béranger, N. Guillot, M. Rafik, Vincent Huard, S. Puget, X. Montagner, M. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, Michel Haond
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引用次数: 401
Abstract
For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.
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