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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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A test controller board for TSS TSS测试控制器板
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143939
K. Kornegay, R. Brodersen
{"title":"A test controller board for TSS","authors":"K. Kornegay, R. Brodersen","doi":"10.1109/GLSV.1991.143939","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143939","url":null,"abstract":"The design of a test controller board for a test support system is presented in this paper. Driven by the SCANTEST software, the test controller board exercises the boundary-scan and scan-path and built-in-self-test hardware implemented on the device under test via a dedicated test-bus. An analog test feature is also described.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Applying Hopfield network to find the minimum cost coverage of a Boolean function 应用Hopfield网络求布尔函数的最小代价覆盖
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143963
P. Chu
{"title":"Applying Hopfield network to find the minimum cost coverage of a Boolean function","authors":"P. Chu","doi":"10.1109/GLSV.1991.143963","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143963","url":null,"abstract":"To find a minimal expression of a Boolean function includes a step to select the minimum cost cover from a set of implicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical for large input data size. In this paper, the author tries to apply neural network approach to solve this problem. He first formulates this problem and then defines an 'energy function' and maps it to a modified Hopfield network, which will automatically search for minima.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132080265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons 一种用于监测和刺激培养神经元动作电位的VLSI外围系统
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143961
M. A. AbuZaid, P. V. Vithalani, W. Gosney, L. L. Howard, G. Gross
{"title":"A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons","authors":"M. A. AbuZaid, P. V. Vithalani, W. Gosney, L. L. Howard, G. Gross","doi":"10.1109/GLSV.1991.143961","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143961","url":null,"abstract":"The authors describe a VLSI peripheral system designed for the analog recording of electric signals from a network of living neurons growing on a glass plate containing 64 microelectrodes. The chip also provides for stimulating the neurons with up to four externally generated signals that can be routed to any of the microelectrodes.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133224658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A framework for 1-D compaction with forbidden region avoidance (VLSI layout) 一种避免禁区的一维压缩框架(VLSI布局)
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143957
Susanne E. Hambrusch, Hung-Yi Tu
{"title":"A framework for 1-D compaction with forbidden region avoidance (VLSI layout)","authors":"Susanne E. Hambrusch, Hung-Yi Tu","doi":"10.1109/GLSV.1991.143957","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143957","url":null,"abstract":"In this paper the authors consider the one-dimensional compaction problem when the layout area contains forbidden regions and the layout components are allowed to move across these regions. Assuming a feasible layout is given containing k forbidden regions and n layout components where the i-th layout component is a rectilinear polygon consisting of upsilon /sub i/ vertical edges, upsilon = Sigma /sub i=1//sup n/ upsilon /sub i/, the authors present an algorithm that determines the positions of the layout components resulting in minimum area in O( sigma log sigma + sigma nlogn) time with an additional O(( upsilon +k)logk+( upsilon + sigma )log upsilon /sub max/) preprocessing time, where upsilon /sub max/=max/sub 1<or=i<or=n/ upsilon /sub i/. The quantity sigma measures the interaction between the layout components and the forbidden regions, sigma <or= upsilon k. The authors also describe variants of this algorithm that makes the running time more problem-dependent. Their algorithms make use of an elegant characterisation of a layout of minimum area.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123866108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transition count testing of CMOS combinational circuits CMOS组合电路的跃迁数测试
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143951
K. S. Manjunath, Damu Radharkrishnan
{"title":"Transition count testing of CMOS combinational circuits","authors":"K. S. Manjunath, Damu Radharkrishnan","doi":"10.1109/GLSV.1991.143951","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143951","url":null,"abstract":"An optimal, robust transition count test generation for testing stuck-open faults in CMOS combinational circuits is presented in this paper. Procedures to optimize conventional stuck-open fault test sets have been developed. The use of fault folding graphs as a tool, to generate optimal test sequences, has been illustrated. Both non-reconvergent and reconvergent, irredundant, circuits are treated,.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Building block layout based on block compaction and two-adjacent-side channel router 基于块压缩和双邻接侧通道路由器的构建块布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143971
S. Yamada, H. Tanabe
{"title":"Building block layout based on block compaction and two-adjacent-side channel router","authors":"S. Yamada, H. Tanabe","doi":"10.1109/GLSV.1991.143971","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143971","url":null,"abstract":"The authors propose a new layout method based on a block compaction and two-adjacent-side channel router for building block VLSI. In this method, the block compaction and global routing are carried out simultaneously and by introducing a new channel router it is possible to avoid unnecessary detour of the wires and reduce the dead space. The present channel routing approach has a remarkable feature that its routability is 100%. Experimental results are shown to compare this method with the previous method.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121251816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test plan generation and concurrent scheduling of tests in the presence of conflicts 在存在冲突的情况下生成测试计划和并发调度测试
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143973
T. C. Wilson, A. Basu, D. Banerji, J. Majithia
{"title":"Test plan generation and concurrent scheduling of tests in the presence of conflicts","authors":"T. C. Wilson, A. Basu, D. Banerji, J. Majithia","doi":"10.1109/GLSV.1991.143973","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143973","url":null,"abstract":"When BILBO tests are being generated and scheduled, resource conflicts between I-paths and tests present many difficulties. The authors explore: how pipelining is limited by potential internal conflicts; ways to promote pipelining during test plan generation and how to incorporate a test into a test phase already containing tests that conflict with it. They do not directly address the general problems of test plan generation or test scheduling. What is offered is insight into the difficulties that (potential) conflicts provide and techniques for handling these difficulties. The insights are primarily theoretical, but the resulting techniques could be viewed as possible extensions to existing methodologies.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128437817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Algorithm independent data flow mapping on a unified VLSI architecture 基于统一VLSI架构的独立于算法的数据流映射
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143944
Subramanian Mahalingham, S. Ganesan
{"title":"Algorithm independent data flow mapping on a unified VLSI architecture","authors":"Subramanian Mahalingham, S. Ganesan","doi":"10.1109/GLSV.1991.143944","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143944","url":null,"abstract":"VLSI architectural unification at primitive hardware and interconnect structure level, is necessary, to cover the methodology of GPVLSI and SPVLSI systems synthesis. The concept of PACUBE array (Programmable Array of Array Adders) leads to this grand unification at macrocell level. The systolic and wavefront arrays have led to a major breakthrough in the design of supercomputing architectures. But the D-flow mapping on these arrays varies greatly depending on the algorithms to be executed, the majority of which are a combination of GIPOP equations. In this paper, both the unifying concept of the P-Arrays and the algorithm independent D-flow mapping on the P-Arrays is presented.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124178392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sequence invariant state machine compiler 序列不变状态机编译器
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143986
D. Buehler, S. Whitaker, J. Canaris
{"title":"Sequence invariant state machine compiler","authors":"D. Buehler, S. Whitaker, J. Canaris","doi":"10.1109/GLSV.1991.143986","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143986","url":null,"abstract":"A CAD tool for automatic generation of VLSI state machines based on a sequence invariant architecture is presented. The program, which is process independent, operates on a flow table input and produces a layout archive. Using an incremental approach for layout also allows subcircuits to be generated.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132969298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gate level representation of ECL circuits for fault modeling 用于故障建模的ECL电路的门级表示
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143989
S. Menon, A. Jayasumana, Y. Malaiya
{"title":"Gate level representation of ECL circuits for fault modeling","authors":"S. Menon, A. Jayasumana, Y. Malaiya","doi":"10.1109/GLSV.1991.143989","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143989","url":null,"abstract":"Bipolar emitter coupled logic (ECL) devices can now be fabricated at high densities and lower power consumption. With the achievement of low power and high densities, ECL technology is expected to be used widely in high performance digital circuits. This necessitates the need for obtaining optimum gate level models for ECL circuits. A simple technique to obtain a gate level model of an ECL circuit is presented. The gate level models obtained for 1-level and 2-level ECL using the transformation rules presented are the same as the fault models that provide higher coverage of physical failures.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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