A framework for 1-D compaction with forbidden region avoidance (VLSI layout)

In this paper the authors consider the one-dimensional compaction problem when the layout area contains forbidden regions and the layout components are allowed to move across these regions. Assuming a feasible layout is given containing k forbidden regions and n layout components where the i-th layout component is a rectilinear polygon consisting of upsilon /sub i/ vertical edges, upsilon = Sigma /sub i=1//sup n/ upsilon /sub i/, the authors present an algorithm that determines the positions of the layout components resulting in minimum area in O( sigma log sigma + sigma nlogn) time with an additional O(( upsilon +k)logk+( upsilon + sigma )log upsilon /sub max/) preprocessing time, where upsilon /sub max/=max/sub 1>