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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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Evaluation of silicon-on-sapphire enhancement JFETs for digital applications 用于数字应用的蓝宝石上硅增强jfet的评价
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143991
I. Talkhan, H. Abdel-Aty-Zohdy
{"title":"Evaluation of silicon-on-sapphire enhancement JFETs for digital applications","authors":"I. Talkhan, H. Abdel-Aty-Zohdy","doi":"10.1109/GLSV.1991.143991","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143991","url":null,"abstract":"Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117247261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dense layouts for series-parallel circuits 密集的串并联电路布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143935
M. Langston, S. Ramachandramurthi
{"title":"Dense layouts for series-parallel circuits","authors":"M. Langston, S. Ramachandramurthi","doi":"10.1109/GLSV.1991.143935","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143935","url":null,"abstract":"The authors address the question 'when do three tracks suffice for the gate matrix layout of series-parallel circuits?' and demonstrate that the rather surprising answer appears to be 'almost always.' This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis characterization of graphs with k-track layouts for any fixed k.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115067153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An experimental environment for design and analysis of global routing heuristics 设计和分析全局路由启发式的实验环境
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143970
J. David, F. Makedon, B. Codenotti, M. Leoncini
{"title":"An experimental environment for design and analysis of global routing heuristics","authors":"J. David, F. Makedon, B. Codenotti, M. Leoncini","doi":"10.1109/GLSV.1991.143970","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143970","url":null,"abstract":"The authors discuss the development and implementation of an object-oriented experimental environment for global routing heuristics in VLSI layout design. This experimental environment has been implemented in both common lisp (with object-oriented extensions) and Smalltalk, providing a user-friendly graphical interface for problem input, output, interaction and modification of the heuristics. Several heuristics have been implemented, some of which use only local information, while others use global information concerning the instance of the problem. All heuristics seem to have good average case performance, and from the results it is concluded that, also on average, multi-turn routings do not provide a significant improvement over one-turn routings.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Study of quaternary logic versus binary logic 四元逻辑与二元逻辑的研究
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143992
A. Gupte, Ashok K. Goel
{"title":"Study of quaternary logic versus binary logic","authors":"A. Gupte, Ashok K. Goel","doi":"10.1109/GLSV.1991.143992","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143992","url":null,"abstract":"The authors deal with the comparison of quaternary and binary logic with reference to entropy, speed of data transmission and data string length QUATLOG, computer simulator developed, demonstrates the relative advantages of employing quaternary logic for data transmission.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128138378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An efficient tabu search algorithm for graph bisectioning 一种高效的图平分禁忌搜索算法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143948
L. Tao, Y. Zhao, K. Thulasiraman, M. Swamy
{"title":"An efficient tabu search algorithm for graph bisectioning","authors":"L. Tao, Y. Zhao, K. Thulasiraman, M. Swamy","doi":"10.1109/GLSV.1991.143948","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143948","url":null,"abstract":"A new algorithm for solving the graph bisectioning problem based on tabu search is proposed. The authors run the tabu search algorithm and the Kernighan-Lin algorithm on the same set of random graphs with 50 to 500 nodes and compare their performances. They demonstrate that for all of the graphs their tabu search algorithm provides lower bisection cost than the Kernighan-Lin algorithm; and for all of the graphs with more than 200 nodes, their tabu search algorithm takes less time than the Kernighan-Lin algorithm.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115853892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A high resolution current stimulating probe for use in neural prostheses 用于神经假体的高分辨率电流刺激探针
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143966
C. Kim, D. Kang, Richard B. Brown, K. Wise
{"title":"A high resolution current stimulating probe for use in neural prostheses","authors":"C. Kim, D. Kang, Richard B. Brown, K. Wise","doi":"10.1109/GLSV.1991.143966","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143966","url":null,"abstract":"The authors describe a high resolution monolithic current stimulating probe which is a multichannel microprobe capable of delivering precisely controlled charge to highly-localized regions of tissue (for example, the auditory nervous system) on a chronic basis. This chip has 8 stimulating sites and provides 7 bits of current level control, that is -126 mu A to +126 mu A with 2 mu A resolution. In order to improve controllability and reduce the cost of the circuitry, the integrated stimulating microprobe is addressable and self-testing. Implemented features include self-test capabilities, a bipolar current forcing scheme for the effective stimulation of the tissue and a user-specified time-out scheme which makes the microstimulator safe. The total number of pads is 14, eight of which are stimulating sites, with the others being used for overall circuit control and power supplies. The chip is designed in an n-epitaxial, p-well, 1.2 mu m, double metal CMOS process with an area of 0.24 mm/sup 2/ excluding bonding pads.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133505745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A linear-time heuristic for rectilinear Steiner trees 线性斯坦纳树的线性时间启发式
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143958
F. D. Lewis, W. C. Pong, N. V. Cleave
{"title":"A linear-time heuristic for rectilinear Steiner trees","authors":"F. D. Lewis, W. C. Pong, N. V. Cleave","doi":"10.1109/GLSV.1991.143958","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143958","url":null,"abstract":"Rectilinear Steiner spanning trees are used in several phases of the VLSI physical design process when collections of terminals must be connected to a common electrical point. The authors present a new linear time heuristic algorithm for generating these rectilinear Steiner trees. They begin with minimal spanning trees and transform those configurations which are never found in the shortest Steiner trees. This decreases the length of the spanning trees. In addition to its speed, the algorithm is straightforward and can be implemented efficiently. Empirical results demonstrate that reductions of over 13% in length are possible, while an average of over 8% reduction is achieved. This compares very favorably to much more complex algorithms. The algorithm is recommended for applications where many spanning trees are needed in a very short time.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124339678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Uni-directional cube-connected cycles 单向立方体连接循环
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143977
S. Bhattacharya, Yoon-Hwa Choi, W. Tsai
{"title":"Uni-directional cube-connected cycles","authors":"S. Bhattacharya, Yoon-Hwa Choi, W. Tsai","doi":"10.1109/GLSV.1991.143977","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143977","url":null,"abstract":"Cube connected cycles (CCC), a popular and layout/efficient alternative to hypercube, can emulate the performance of hypercube for many parallel algorithms. Recently, interconnection networks based on simplex links rather than duplex have been proposed. The uni-directional architectures have layout advantages and reduces complexity of each processing element (PE). The authors propose directed cube connected cycles (DCCC) as a uni-directional alternative to CCC. They have developed PE-to-PE routing algorithm for DCCC. A method for porting algorithms (designed to run on bi-directional CCC) to DCCC is provided. The extent of slowdown due to using simplex links is evaluated. They also provide loop embedding on DCCC. DCCC is found competitive to CCC in algorithmic performance though DCCC is much layout inexpensive.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123644733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Topological via minimization and routing 拓扑通过最小化和路由
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143969
A. Abdullah, S. Sastry
{"title":"Topological via minimization and routing","authors":"A. Abdullah, S. Sastry","doi":"10.1109/GLSV.1991.143969","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143969","url":null,"abstract":"The authors consider topological via minimization (TVM) and topological routing (TR) of a two-point nets on two layers. They present a graph coloring technique for via minimization and also use it to derive bounds on the number of vias. The bounds are net intersection dependent. The complexity of coloring procedure is O(n/sup 2/). The coloring procedure shows an abrupt drop in complexity, when intersection density is about 20%. For TR an O(n/sup 4/) algorithm is presented which guarantees at most one via per net. Using the authors' TVM and TR procedures, constraints such as assignment of nets to a particular layer, assignment of via to a particular net, and via density control can be implemented.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128874797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Genetic synthesis: performance-driven logic synthesis using genetic evolution 遗传综合:利用遗传进化进行性能驱动的逻辑综合
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143985
R. Vemuri, R. Vemuri
{"title":"Genetic synthesis: performance-driven logic synthesis using genetic evolution","authors":"R. Vemuri, R. Vemuri","doi":"10.1109/GLSV.1991.143985","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143985","url":null,"abstract":"The authors present a system for constraint-directed synthesis of logic circuits. The heart of the system is a genetic synthesis algorithm capable of searching the design space in the presence of user-specified constraints on performance attributes such as the area, critical path length, number of gates, wires and any other attribute which can be procedurally described. Three experimental results are presented and discussed.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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