{"title":"用于数字应用的蓝宝石上硅增强jfet的评价","authors":"I. Talkhan, H. Abdel-Aty-Zohdy","doi":"10.1109/GLSV.1991.143991","DOIUrl":null,"url":null,"abstract":"Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Evaluation of silicon-on-sapphire enhancement JFETs for digital applications\",\"authors\":\"I. Talkhan, H. Abdel-Aty-Zohdy\",\"doi\":\"10.1109/GLSV.1991.143991\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143991\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143991","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Evaluation of silicon-on-sapphire enhancement JFETs for digital applications
Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications.<>