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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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A parallel algorithm for logic simulation on transputer networks 计算机网络逻辑仿真的并行算法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143974
S. Srinivas, A. Basu, A. Paulraj, L. Patnaik
{"title":"A parallel algorithm for logic simulation on transputer networks","authors":"S. Srinivas, A. Basu, A. Paulraj, L. Patnaik","doi":"10.1109/GLSV.1991.143974","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143974","url":null,"abstract":"The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with communication, thereby reducing the communication overhead. It also attempts even distribution of load in order to reduce processor idle time. The algorithm possesses the advantages of ease of implementation and ease of extension to incorporate additional parameters for simulation. Performance results of the algorithm are given.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors 调制掺杂异质结场效应晶体管横向延迟的建模
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143988
W. Xu, Ashok K. Goel
{"title":"Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors","authors":"W. Xu, Ashok K. Goel","doi":"10.1109/GLSV.1991.143988","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143988","url":null,"abstract":"The authors have developed a computer-efficient algorithm and the related CAD oriented software to calculate the transverse propagation delay in a MODFET. The model has been used to study the dependence of these delays on the various MODFET parameters. The results can be utilized for the optimization of high-speed circuits.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116137271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two-dimensional multirate systolic array design for artificial neural networks 人工神经网络二维多速率收缩阵列设计
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143964
E. Khan, N. Ling
{"title":"Two-dimensional multirate systolic array design for artificial neural networks","authors":"E. Khan, N. Ling","doi":"10.1109/GLSV.1991.143964","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143964","url":null,"abstract":"In this paper a novel design of neural networks using 2-dimensional systolic array is proposed. Two techniques are applied in the design, namely, 2-dimensional pipelining and multirate processing (2 level clocking). 2-dimensional pipelining operation gives significant improvement in computation time compared to the currently known 1D and 2D systolic implementation schemes. Besides, multirate clocking is used so that weights (synapses) can be transmitted and passed systolically in a rate much higher than activation voltages, to achieve maximum array throughput and to eliminate global interconnections present in many array (including systolic) designs (thus reducing synchronization and propagation delay problems). This scheme of passing weights also saves area significantly since local storage area for the weights can be reduced. The design is applied to the implementation of a Hopfield neural net.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Area efficient binary tree layout 面积高效二叉树布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143936
S. Bhattacharya, W. Tsai
{"title":"Area efficient binary tree layout","authors":"S. Bhattacharya, W. Tsai","doi":"10.1109/GLSV.1991.143936","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143936","url":null,"abstract":"H-Tree layout for binary trees can utilize only 50% of the available nodes. Improved binary tree layout techniques have been developed only after relaxing the rectangular grid model assumptions. The authors propose an area-efficient VLSI layout strategy for full binary trees without relaxing the rectangular grid model assumptions. For a height-5 full binary tree they developed a (5*8) layout pattern on an ad hoc basis. This tile is more area efficient than an equivalent H-Tree layout of a height-5 full binary tree. Using this tile, higher level trees are built in a way identical to H-Tree. The area efficiency remains for any level of tree construction. The proposed layout has an improved aspect ratio compared with H-Tree and features a reduced length of the longest link.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testability profile estimation of VLSI circuits from fault coverage 基于故障覆盖的超大规模集成电路可测试性轮廓估计
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143972
H. Farhat, H. Saidian
{"title":"Testability profile estimation of VLSI circuits from fault coverage","authors":"H. Farhat, H. Saidian","doi":"10.1109/GLSV.1991.143972","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143972","url":null,"abstract":"The authors present a new method of estimating the testability profile of a circuit from its random fault coverage data. They have recently developed a relationship between fault coverage and testability profile. However, their testability profile estimates were based on unknown distribution of input vectors and used Bayes theorem with a priori uniform detection probability distribution. The testability profile is modeled as a series of impulse functions and the strength of each estimated from fault coverage data. Experimental results given on three of the large ISCAS benchmark circuits reflect the accuracy of these estimates. Applications include: coverage prediction from testability analysis, prediction of test length, and test generation by fault sampling.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators NCHIPSIM - NMOS芯片性能指标的微电脑模拟器
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143990
Ashok K. Goel, F. Schuermeyer
{"title":"'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators","authors":"Ashok K. Goel, F. Schuermeyer","doi":"10.1109/GLSV.1991.143990","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143990","url":null,"abstract":"The authors have developed a computer simulator called 'NCHIPSIM' which can be used to simulate with a microcomputer the performance indicators of an integrated circuit microprocessor chip based on silicon NMOS technology. In addition to predicting the various chip performance indicators such as its size, power consumption, maximum clock frequency, computational capacity, functional throughput and the fabrication yield for a chip with given technology parameters, the simulator can also be used to simulate the dependence of any of the performance indicators based on the technology feature size as well as on the integration level of the chip.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126488113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An architecture design using VLSI building blocks for dynamic programming neural networks 采用VLSI构建块进行动态规划神经网络的体系结构设计
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143962
C. Chiu, M. Shanblatt
{"title":"An architecture design using VLSI building blocks for dynamic programming neural networks","authors":"C. Chiu, M. Shanblatt","doi":"10.1109/GLSV.1991.143962","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143962","url":null,"abstract":"An architecture for dynamic programming neural networks is presented. The architecture is based on a building block paradigm in which the network is constructed from neuron array and weight assignment chips. Because of its simple and regular structure, the architecture is a feasible implementation for dynamic programming neural networks with current VLSI technology. Moreover, this architecture can be further extended to other Hopfield-Tank type networks.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128005713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
I/O bound binary tree layout I/O绑定二叉树布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143938
S. Bhattacharya, Yoon-Hwa Choi, W. Tsai
{"title":"I/O bound binary tree layout","authors":"S. Bhattacharya, Yoon-Hwa Choi, W. Tsai","doi":"10.1109/GLSV.1991.143938","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143938","url":null,"abstract":"The authors propose a VLSI layout strategy for a full binary tree. This layout can support more border leaf processing elements (PEs) and thus can give a higher I-O bandwidth. It is superior to the H-tree layout in terms of the number of boundary leaves. The approach uses H-tree pattern for constructing subtree layouts and then combines a number of such subtrees following standard tree style to get a larger sized tree layout. Finally at the top level H-tree layout style is used to get the overall tree layout. Different I/O bandwidths can be obtained varying the subtree height. The authors derive expression for layout area, longest link and aspect ratio of the chip. It is observed that I/O bandwidth can be significantly increased without much area overhead using this approach.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121421410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An approach for multilevel logic cell optimization in module generators 模块生成器中多级逻辑单元优化方法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143980
P. Poechmueller, M. Glesner
{"title":"An approach for multilevel logic cell optimization in module generators","authors":"P. Poechmueller, M. Glesner","doi":"10.1109/GLSV.1991.143980","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143980","url":null,"abstract":"The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128965077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS output buffer waveshaping CMOS输出缓冲器整形
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143987
L. Albertson, S. Whitaker, R. Merrell
{"title":"CMOS output buffer waveshaping","authors":"L. Albertson, S. Whitaker, R. Merrell","doi":"10.1109/GLSV.1991.143987","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143987","url":null,"abstract":"The authors report a novel design technique to reduce output switching noise in CMOS VLSI circuits. The technique is based on analysis of the RLC equivalent circuit of the output driver stage. SPICE simulations verify the method's effectiveness and a test circuit is being submitted to MOSIS for fabrication.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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