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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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Routing non-convex grids without holes 路由无孔的非凸网格
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143959
Dee Parks, M. Truszczynski
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引用次数: 1
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits VLSI电路中内置自检的区域时间权衡集成方法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143994
A. Basu, T. C. Wilson, D. Banerji, J. Majithia
{"title":"Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits","authors":"A. Basu, T. C. Wilson, D. Banerji, J. Majithia","doi":"10.1109/GLSV.1991.143994","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143994","url":null,"abstract":"The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116752553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new approach to timing driven partitioning of combinational logic 时序驱动组合逻辑划分的新方法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1900-01-01 DOI: 10.1109/GLSV.1991.143949
N. Wehn, M. Glesner
{"title":"A new approach to timing driven partitioning of combinational logic","authors":"N. Wehn, M. Glesner","doi":"10.1109/GLSV.1991.143949","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143949","url":null,"abstract":"The authors present a new approach to timing driven partitioning of combinational logic. Instead of accessing a predefined library, complex gates based on the line-of-diffusion layout style are automatically synthesized. A new timing model for complex gates is presented which permits a fast pattern independent timing analysis with a deviation of less than 10% and two to three orders of magnitude faster than the exact SPICE simulation taking into account all parasitics and signal slopes. To improve the overall timing, a heuristic is presented which is based on iterative partitioning techniques for complex gates. The overall performance is demonstrated on several examples.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel digital VLSI GaAs FET circuits for low power and high functional yield 新型低功耗、高功能良率的数字VLSI GaAs FET电路
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1900-01-01 DOI: 10.1109/GLSV.1991.143978
A. Eldin
{"title":"Novel digital VLSI GaAs FET circuits for low power and high functional yield","authors":"A. Eldin","doi":"10.1109/GLSV.1991.143978","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143978","url":null,"abstract":"The complexity of GaAs FET VLSI circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, novel digital GaAs FET circuits are presented that eliminate the DC power dissipation, reduce the area to 50% of that of the conventional static circuit and its larger tolerance to device parameters variations, results in higher functional yield.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127109772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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