VLSI电路中内置自检的区域时间权衡集成方法

[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI:10.1109/GLSV.1991.143994

A. Basu, T. C. Wilson, D. Banerji, J. Majithia

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摘要

作者使用BIST的BILBO方法解决了VLSI电路中区域时间权衡的问题。这个问题已得到综合处理。提出了两种不同的方法，整数线性规划和图论

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Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented.<>

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[1991] Proceedings. First Great Lakes Symposium on VLSI

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