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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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A CAD tool for designing large, fault-tolerant VLSI arrays 用于设计大型、容错VLSI阵列的CAD工具
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143955
P. Poechmueller, G. Sharma, M. Glesner
{"title":"A CAD tool for designing large, fault-tolerant VLSI arrays","authors":"P. Poechmueller, G. Sharma, M. Glesner","doi":"10.1109/GLSV.1991.143955","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143955","url":null,"abstract":"The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129895292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A VLSI implementation of a state variable filter algorithm 一种状态变量滤波算法的VLSI实现
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143956
H. Herpel, P. Windirsch, M. Glesner, J. Führer, J. Busshardt
{"title":"A VLSI implementation of a state variable filter algorithm","authors":"H. Herpel, P. Windirsch, M. Glesner, J. Führer, J. Busshardt","doi":"10.1109/GLSV.1991.143956","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143956","url":null,"abstract":"The authors present a digital signal processor (DSP) architecture whose powerful CPU is optimized to solve a state variable filter algorithm, but is not limited to that application. State variable filters perform low pass filtering and generate the derivatives of the filtered signal. These signals are used in systems for real-time process identification. In order to minimize the number of components, program and data memory, timers, and peripheral control logic are integrated on the DSP chip. Software development for this DSP is supported by an assembler, simulator and high level language compiler. In addition to the presentation of the architecture, a design methodology is introduced which uses rapid prototyping techniques to verify system design and algorithms in their real-time environment.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A massively parallel and versatile architecture for computer vision 一种用于计算机视觉的大规模并行和通用架构
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143945
A. Deb, N. Ling
{"title":"A massively parallel and versatile architecture for computer vision","authors":"A. Deb, N. Ling","doi":"10.1109/GLSV.1991.143945","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143945","url":null,"abstract":"A massively parallel architecture for vision that can be efficiently implemented as a dense and regular VLSI circuit is proposed. It consists of locally connected array of simple processors possessing certain capabilities, making it possible to form a complete vision system for binary images, that can operate in real time. For low level processing both a systolic implementation on a 2D array, as well as a non-systolic 'retinotopic' processing is possible. For the intermediate level, support for pyramidal hierarchy on the array is provided. To facilitate high level vision processing on the same architecture both AI, as well as the binary neural network approaches are applied.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131997629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of fault-tolerant sequential circuits using programmable logic arrays 使用可编程逻辑阵列的容错顺序电路的实现
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143954
N. Misra, Ashok K. Goel
{"title":"Implementation of fault-tolerant sequential circuits using programmable logic arrays","authors":"N. Misra, Ashok K. Goel","doi":"10.1109/GLSV.1991.143954","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143954","url":null,"abstract":"An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area in terms of the fusible links blown to realize the state machine using PLAs.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132309343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A hierarchical multi-level test generation system 分层多级测试生成系统
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143942
A. Lioy, M. Poncino
{"title":"A hierarchical multi-level test generation system","authors":"A. Lioy, M. Poncino","doi":"10.1109/GLSV.1991.143942","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143942","url":null,"abstract":"The authors describe a multi-level ATPG system which handles circuits consisting of 'switch' transistors, Boolean gates, and open-output gates (i.e., tristate, open-collector, open-emitter). Both combinational and synchronous sequential circuits are supported, with provision for full-scan, partial-scan, and non-scan design. The most remarkable features of the system are an unified approach to test generation (suitable to compiled-code implementation) and automatic extraction of hierarchy.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133774487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transforming disfigured and disoriented areas into routable switchboxes 将毁容和迷失方向的区域转变为可路由的开关箱
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143946
M. Starkey, Tony M. Carter
{"title":"Transforming disfigured and disoriented areas into routable switchboxes","authors":"M. Starkey, Tony M. Carter","doi":"10.1109/GLSV.1991.143946","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143946","url":null,"abstract":"Routing an entire VLSI circuit requires partitioning the circuit (routing area) into smaller, localized routing areas. Using non-rectangular, rotated switchbox shapes (and therefore non-Manhattan routing layout) has the potential to simplify the partitioning of the circuit into routable areas and to use 'dead space' on a chip for routing. The method described in this paper for generating non-rectangular, rotated switchboxes borrows ideas from computer graphics.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134005634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Four layer wiring using adjacent-layer vias 采用邻接层过孔的四层布线
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143960
Tuang-Kuang Wu, M. Brady
{"title":"Four layer wiring using adjacent-layer vias","authors":"Tuang-Kuang Wu, M. Brady","doi":"10.1109/GLSV.1991.143960","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143960","url":null,"abstract":"An algorithm is presented which, given a two-dimensional wire layout in knock-knee mode, produces a legal wiring (layer-assignment) using only adjacent-layer vias and at most four layers. The previous four-layer wiring algorithm requires technologically impractical vias between non-adjacent layers. This algorithm has important implications for practical automatic wire routing, since many knock-knee layout algorithms rely on the four-layer wiring technique to complete their routing.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122343698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power CMOS correlator 低功耗CMOS相关器
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143953
J. Canaris, S. Whitaker
{"title":"A low power CMOS correlator","authors":"J. Canaris, S. Whitaker","doi":"10.1109/GLSV.1991.143953","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143953","url":null,"abstract":"A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable. The correlator was designed to Mil Spec, 3 sigma Worst Case Speed parameters.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116402561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Discrete Fourier transform processors using CORDIC 使用CORDIC的离散傅里叶变换处理器
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143976
Jeong-A Lee, Kiseon Kim
{"title":"Discrete Fourier transform processors using CORDIC","authors":"Jeong-A Lee, Kiseon Kim","doi":"10.1109/GLSV.1991.143976","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143976","url":null,"abstract":"The author presents an analysis of the cost-effectiveness of discrete Fourier transform processors, based on CORDIC modules such as the bit-serial, parallel with non-redundant and redundant arithmetic, and pipelined. The performance of each processor is analyzed with respect to the time to process one frequency output and the number of modules required. It is shown that the CORDIC-based DFT processor is a prospective solution in VLSI to be used for a wide range of input bit rate.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of fail-safe CMOS logic circuits 故障安全CMOS逻辑电路的设计
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143993
V. Bobin, S. Whitaker
{"title":"Design of fail-safe CMOS logic circuits","authors":"V. Bobin, S. Whitaker","doi":"10.1109/GLSV.1991.143993","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143993","url":null,"abstract":"Design techniques to make CMOS logic circuits fail-safe are reported. The set of transistor stuck-on and stuck-open faults, signal lines stuck-at faults, and bridging faults is partitioned into two classes of faults. Fail-safe property is maintained for multiple faults within a class. Limited fault tolerance capability is introduced as a by-product.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127305840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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