A massively parallel and versatile architecture for computer vision

A. Deb, N. Ling
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引用次数: 2

Abstract

A massively parallel architecture for vision that can be efficiently implemented as a dense and regular VLSI circuit is proposed. It consists of locally connected array of simple processors possessing certain capabilities, making it possible to form a complete vision system for binary images, that can operate in real time. For low level processing both a systolic implementation on a 2D array, as well as a non-systolic 'retinotopic' processing is possible. For the intermediate level, support for pyramidal hierarchy on the array is provided. To facilitate high level vision processing on the same architecture both AI, as well as the binary neural network approaches are applied.<>
一种用于计算机视觉的大规模并行和通用架构
提出了一种大规模并行视觉架构,可以有效地实现为密集和规则的VLSI电路。它由具有一定功能的局部连接的简单处理器阵列组成,从而可以形成一个完整的二值图像视觉系统,可以实时运行。对于低水平的处理,既可以在二维阵列上实现收缩期,也可以进行非收缩期的“视网膜置换”处理。对于中间级别,提供了对数组的金字塔层次结构的支持。为了在同一架构上促进高层次的视觉处理,应用了人工智能和二元神经网络方法
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