分层多级测试生成系统

[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI:10.1109/GLSV.1991.143942

A. Lioy, M. Poncino

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引用次数: 0

摘要

作者描述了一个多级ATPG系统，该系统处理由“开关”晶体管、布尔门和开输出门(即三态、开集电极、开发射极)组成的电路。支持组合和同步顺序电路，并提供全扫描，部分扫描和非扫描设计。该系统最显著的特点是统一的测试生成方法(适用于编译代码实现)和自动提取层次结构。

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A hierarchical multi-level test generation system

The authors describe a multi-level ATPG system which handles circuits consisting of 'switch' transistors, Boolean gates, and open-output gates (i.e., tristate, open-collector, open-emitter). Both combinational and synchronous sequential circuits are supported, with provision for full-scan, partial-scan, and non-scan design. The most remarkable features of the system are an unified approach to test generation (suitable to compiled-code implementation) and automatic extraction of hierarchy.<>

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[1991] Proceedings. First Great Lakes Symposium on VLSI

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