A CAD tool for designing large, fault-tolerant VLSI arrays

The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.<>