A hierarchical multi-level test generation system

Abstract

The authors describe a multi-level ATPG system which handles circuits consisting of 'switch' transistors, Boolean gates, and open-output gates (i.e., tristate, open-collector, open-emitter). Both combinational and synchronous sequential circuits are supported, with provision for full-scan, partial-scan, and non-scan design. The most remarkable features of the system are an unified approach to test generation (suitable to compiled-code implementation) and automatic extraction of hierarchy.<>