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[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

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On the generalized channel definition problem 关于广义信道定义问题
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143947
T. Gonzalez, M. Razzazi
{"title":"On the generalized channel definition problem","authors":"T. Gonzalez, M. Razzazi","doi":"10.1109/GLSV.1991.143947","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143947","url":null,"abstract":"The generalized channel definition problem has been modeled as the following partition problem. Let RP be a boundary defined by a rectilinear polygon in E/sup 2/ and let H be a set of holes defined by disjoint rectilinear polygons inside RP. For IP=(RP,H), p(IP) is used to denote the length of the line segments that define RP plus the sum of the length of the line segments that define the holes in H. The authors consider the RP-RP problem in which RP is partitioned into rectangles by introducing a set of orthogonal line segments with least total length. Then m(IP) is used to denote the total length of the partitioning segments in an optimal solution to IP. The problem of finding m(IP) given IP is NP-hard. In this paper an O(n log n) approximation algorithm is presented for the RP-RP problem that generates solutions with length at most 2.5p(IP)+6m(IP), where n is the total number of segments in RP and H.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126022897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A reconstructive approach to automated design synthesis 自动化设计综合的重构方法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143984
Michael R. Wick, B. D. Britt
{"title":"A reconstructive approach to automated design synthesis","authors":"Michael R. Wick, B. D. Britt","doi":"10.1109/GLSV.1991.143984","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143984","url":null,"abstract":"Derivational Analogy is a technique used to adapt a previous design plan to solve a new problem. However, derivational analogy requires that this design plan be saved at the time of design. Design plans are generally not available unless design occurred with an automated design assistant, which could capture the details of the design process. Some design assistants do not have this ability, and many designs exist which were developed without an automated assistant. A method is proposed for recreating a design plan for a design, using design rationale information. Rationales are used to choose from possible design decisions, and to bias the design plan towards the new problem. This method enables the use of a design in derivational analogy even when the design plan is not available and demonstrates a significant potential for rationales in automated design. The authors discuss in detail the knowledge required and techniques applied for automated reconstruction of deviational histories.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126166078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On wiring overlap layouts 关于布线重叠布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143937
C. Chiang
{"title":"On wiring overlap layouts","authors":"C. Chiang","doi":"10.1109/GLSV.1991.143937","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143937","url":null,"abstract":"A layout model called vertical-two-overlap is introduced. The following results are established for an arbitrary vertical-two-overlap layout W with area A. 1. A linear time algorithm for obtaining a two-layer wiring of W, if one exists, is devised. Also, by increasing the area to at most 2A a two-layer wirable layout is obtained. 2. To decide three-layer wirability of an arbitrary vertical-two-overlap layout is NP-complete. However, W can be converted into a three-layer wirable layout with area at most 3/2 A. 3. W is always four-layer wirable and a four-layer wiring thereof can be constructed in O(A) time.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128436242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI routing on the pipelined hypercube and related networks 管道超立方体及相关网络上的VLSI路由
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143933
J. JáJá
{"title":"VLSI routing on the pipelined hypercube and related networks","authors":"J. JáJá","doi":"10.1109/GLSV.1991.143933","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143933","url":null,"abstract":"The author presents parallel algorithms for several important combinatorial problems related to VLSI routing. These algorithms achieve linear speed-ups on the pipelined hypercube, and provably optimal speed-ups on the shuffle-exchange and the cube-connected-cycles, for any number p of processors satisfying 1 <or= p <or= n/log/sup 3/n (log logn)/sup 2/, where n is the input size. The lower bound results are established under no restriction on how the input is mapped into the local memories of the different processors.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125565574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing VLSI systolic arrays with complex processing elements 设计具有复杂处理元件的VLSI收缩阵列
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143967
Chang Nian Zhang, Alen George Law, Ali Rezazadeh
{"title":"Designing VLSI systolic arrays with complex processing elements","authors":"Chang Nian Zhang, Alen George Law, Ali Rezazadeh","doi":"10.1109/GLSV.1991.143967","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143967","url":null,"abstract":"The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing element design and achieving higher throughput.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129082638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimal test set for stuck-at faults in VLSI 超大规模集成电路卡滞故障的最优测试集
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143950
K. S. Manjunath, S. Whitaker
{"title":"Optimal test set for stuck-at faults in VLSI","authors":"K. S. Manjunath, S. Whitaker","doi":"10.1109/GLSV.1991.143950","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143950","url":null,"abstract":"Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HADES-high-level architecture development and exploration system hades高级建筑开发探索系统
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143995
P. Poechmueller, M. Held, N. Wehn, M. Glesner
{"title":"HADES-high-level architecture development and exploration system","authors":"P. Poechmueller, M. Held, N. Wehn, M. Glesner","doi":"10.1109/GLSV.1991.143995","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143995","url":null,"abstract":"The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. For final structural synthesis an advanced tool based on genetic algorithms is provided. Layout synthesis is assumed to be performed by available tools like the GENESIL silicon compiler.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Gate matrix layout based on hierarchical net-list representations 基于分层网络表表示的门矩阵布局
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143981
Shigeki Yamada, K. Yamazaki
{"title":"Gate matrix layout based on hierarchical net-list representations","authors":"Shigeki Yamada, K. Yamazaki","doi":"10.1109/GLSV.1991.143981","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143981","url":null,"abstract":"The authors propose a hierarchical gate matrix layout algorithm based on a new net-list. It has remarkable features such that logical equivalence is considered, and the drawback of the greedy method can be overcome by using special features of multiterminal nets. Experimental results for CMOS circuits are far superior to those obtained by another published method.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129343038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The 60 degrees grid : routing channels in width d/ square root 3 60度网格:路由通道宽度为d/根号3
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143968
K. D. Powers, D. J. Brown, M. Brady
{"title":"The 60 degrees grid : routing channels in width d/ square root 3","authors":"K. D. Powers, D. J. Brown, M. Brady","doi":"10.1109/GLSV.1991.143968","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143968","url":null,"abstract":"The 60 degrees grid consists of vertical columns and diagonal tracks running at slopes of +or-30 degrees . This model offers a potentially large reduction in channel width, without resorting to wire overlap. For a channel routing problem with density d, the availability of the diagonal tracks leads to a lower bound of d/ square root 3. The authors present two near-optimal channel routing algorithms. The first uses 5 layers and always routes in width at most d/ square root 3+ square root 3. The second algorithm uses at most 4 layers and routes in width omega , where d/ square root 3+O(1)<or= omega <or=d/ square root 3+O( square root d).<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An innovative user interface for fault simulation systems 一个创新的用户界面故障模拟系统
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143941
P. Montessoro
{"title":"An innovative user interface for fault simulation systems","authors":"P. Montessoro","doi":"10.1109/GLSV.1991.143941","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143941","url":null,"abstract":"Fault simulation is a heavy task, and large experiments may require several hours to complete. So far, therefore, fault simulation has been considered a batch task. In this paper some innovative design concepts for the user interface are presented, to provide easy and powerful control of the experiments. The Creator's user interface is an example of actual implementation. It can control one or more simulation experiments running on the same computer or on different machines in a computer network, and each simulation can be dynamically switched between interactive and batch mode. The system is based on a network communication tool, specially developed, and on the X-11 standard for the graphical features.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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