Optimal test set for stuck-at faults in VLSI

Abstract

Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.<>