设计具有复杂处理元件的VLSI收缩阵列

[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI:10.1109/GLSV.1991.143967

Chang Nian Zhang, Alen George Law, Ali Rezazadeh

{"title":"设计具有复杂处理元件的VLSI收缩阵列","authors":"Chang Nian Zhang, Alen George Law, Ali Rezazadeh","doi":"10.1109/GLSV.1991.143967","DOIUrl":null,"url":null,"abstract":"The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing element design and achieving higher throughput.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Designing VLSI systolic arrays with complex processing elements\",\"authors\":\"Chang Nian Zhang, Alen George Law, Ali Rezazadeh\",\"doi\":\"10.1109/GLSV.1991.143967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing element design and achieving higher throughput.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

将时空表示方法扩展到将复杂运算映射到收缩数组的算法中。提出了一些新的技术，包括算法改进和硬件共享的处理元素的收缩阵列。与现有技术相比，该方法提供了一种简单有效的方法，降低了加工元件设计的复杂性，实现了更高的吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Designing VLSI systolic arrays with complex processing elements

The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing element design and achieving higher throughput.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

[1991] Proceedings. First Great Lakes Symposium on VLSI

自引率

0.00%

发文量