{"title":"超大规模集成电路卡滞故障的最优测试集","authors":"K. S. Manjunath, S. Whitaker","doi":"10.1109/GLSV.1991.143950","DOIUrl":null,"url":null,"abstract":"Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Optimal test set for stuck-at faults in VLSI\",\"authors\":\"K. S. Manjunath, S. Whitaker\",\"doi\":\"10.1109/GLSV.1991.143950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.<>