{"title":"关于布线重叠布局","authors":"C. Chiang","doi":"10.1109/GLSV.1991.143937","DOIUrl":null,"url":null,"abstract":"A layout model called vertical-two-overlap is introduced. The following results are established for an arbitrary vertical-two-overlap layout W with area A. 1. A linear time algorithm for obtaining a two-layer wiring of W, if one exists, is devised. Also, by increasing the area to at most 2A a two-layer wirable layout is obtained. 2. To decide three-layer wirability of an arbitrary vertical-two-overlap layout is NP-complete. However, W can be converted into a three-layer wirable layout with area at most 3/2 A. 3. W is always four-layer wirable and a four-layer wiring thereof can be constructed in O(A) time.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On wiring overlap layouts\",\"authors\":\"C. Chiang\",\"doi\":\"10.1109/GLSV.1991.143937\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A layout model called vertical-two-overlap is introduced. The following results are established for an arbitrary vertical-two-overlap layout W with area A. 1. A linear time algorithm for obtaining a two-layer wiring of W, if one exists, is devised. Also, by increasing the area to at most 2A a two-layer wirable layout is obtained. 2. To decide three-layer wirability of an arbitrary vertical-two-overlap layout is NP-complete. However, W can be converted into a three-layer wirable layout with area at most 3/2 A. 3. W is always four-layer wirable and a four-layer wiring thereof can be constructed in O(A) time.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143937\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143937","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A layout model called vertical-two-overlap is introduced. The following results are established for an arbitrary vertical-two-overlap layout W with area A. 1. A linear time algorithm for obtaining a two-layer wiring of W, if one exists, is devised. Also, by increasing the area to at most 2A a two-layer wirable layout is obtained. 2. To decide three-layer wirability of an arbitrary vertical-two-overlap layout is NP-complete. However, W can be converted into a three-layer wirable layout with area at most 3/2 A. 3. W is always four-layer wirable and a four-layer wiring thereof can be constructed in O(A) time.<>
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