Novel digital VLSI GaAs FET circuits for low power and high functional yield

Abstract

The complexity of GaAs FET VLSI circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, novel digital GaAs FET circuits are presented that eliminate the DC power dissipation, reduce the area to 50% of that of the conventional static circuit and its larger tolerance to device parameters variations, results in higher functional yield.<>