Area efficient binary tree layout

Abstract

H-Tree layout for binary trees can utilize only 50% of the available nodes. Improved binary tree layout techniques have been developed only after relaxing the rectangular grid model assumptions. The authors propose an area-efficient VLSI layout strategy for full binary trees without relaxing the rectangular grid model assumptions. For a height-5 full binary tree they developed a (5*8) layout pattern on an ad hoc basis. This tile is more area efficient than an equivalent H-Tree layout of a height-5 full binary tree. Using this tile, higher level trees are built in a way identical to H-Tree. The area efficiency remains for any level of tree construction. The proposed layout has an improved aspect ratio compared with H-Tree and features a reduced length of the longest link.<>