发布求助
文献互助 智能选刊 最新文献

[1991] Proceedings. First Great Lakes Symposium on VLSI最新文献

筛选
英文 中文
Interlocked test generation and digital hardware synthesis 联锁测试生成和数字硬件合成
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143932
F. Hill
{"title":"Interlocked test generation and digital hardware synthesis","authors":"F. Hill","doi":"10.1109/GLSV.1991.143932","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143932","url":null,"abstract":"Digital hardware synthesis implies the use of clock mode register transfer level descriptions. A major feature of this approach to synthesis is the possibility of integrating test generation into the design and synthesis process. Preliminary synthesis makes it possible to link test search at the function level to fault enumeration at the network level. A recently developed backward state justification search has eliminated the final bottleneck in automatic test generation.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
General and efficient multiple list traversal for concurrent fault simulation 通用高效的多表遍历并行故障仿真
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143940
P. Montessoro, S. Gai
{"title":"General and efficient multiple list traversal for concurrent fault simulation","authors":"P. Montessoro, S. Gai","doi":"10.1109/GLSV.1991.143940","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143940","url":null,"abstract":"Accuracy, generality and efficiency are critical factors when fault simulation of VLSI circuits is the target. The concurrent algorithm is the only solution when generality and accuracy is required. Its differential representation of the network status saves memory and CPU time, but due to its complexity the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. In the paper the minimal information concept is discussed, and its applications to the key algorithms for concurrent event-driven simulation are shown. New advanced generalized techniques for multiple list traversal (MLT), trigger inhibition, fraternal event processing, list events, edge sensitive inputs, compile-driven evaluation functions, functional fault sources and clock suppression are presented for the first time in a truly unified context.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"189 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120940387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Proving finite state machines correct with an automaton-based method 用基于自动机的方法证明有限状态机的正确性
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143975
P. Camurati, M. Gilli, P. Prinetto, M. Reorda
{"title":"Proving finite state machines correct with an automaton-based method","authors":"P. Camurati, M. Gilli, P. Prinetto, M. Reorda","doi":"10.1109/GLSV.1991.143975","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143975","url":null,"abstract":"The authors present a method to prove equivalence of a pair of FSMs, described at the gate level with D-type flip-flops and a reset signal available to bring them into the all-zero initial state. This method restricts investigation to that minimum subset of states that can be reached from the reset condition and are necessary to reach the goal. The equivalence condition is expressed in theoretical terms within the framework of the product machine. Without any loss of information, it is possible to reduce the product machine to a deterministic finite automaton (DFA). considerably reducing the number of states. The DFA is dynamically built by an explicit enumeration algorithm and, in general, only a very small part of the automaton is actually considered. The equivalence condition becomes a proof of the reachability of the DFA's final state. Search is performed in breadth-first. Experimental results on some pairs of ISCAS'89 circuits are reported.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and evaluation of fault tolerance techniques for highly parallel architectures 高度并行架构容错技术的设计与评价
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143934
J. Abraham
{"title":"Design and evaluation of fault tolerance techniques for highly parallel architectures","authors":"J. Abraham","doi":"10.1109/GLSV.1991.143934","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143934","url":null,"abstract":"Summary form only given. The author discusses fault tolerance techniques for computer systems, including a new technique, which he calls algorithm-based fault tolerance, for error detection and correction when computations are performed using multiple processor systems. The technique uses knowledge about the algorithm to reduce the amount of overhead necessary for fault tolerance. This is done by appropriately encoding the data and tailoring the algorithms to operate on the encoded data and produce encoded output data. Examples are given of applications including matrix operations, fast Fourier transforms, and computation of eigenvalues.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An algebraic approach to test generation for sequential circuits 时序电路测试生成的代数方法
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143952
A. Lioy, E. Macii, A. Meo, M. Reorda
{"title":"An algebraic approach to test generation for sequential circuits","authors":"A. Lioy, E. Macii, A. Meo, M. Reorda","doi":"10.1109/GLSV.1991.143952","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143952","url":null,"abstract":"The authors describe an algebraic algorithm for automatic test pattern generation for sequential circuits. Three innovative concepts have been introduced in order to reduce the computational time required for pattern generation. These are: firstly, circuit partitioning in fanout-free regions; then, computation of observability and excitability functions for state propagation and justification; and finally, assignment of an observability and an excitability order to each node of the decision tree, for fast test pattern detection of each fault.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116388851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics 从MOS电路原理图中生成符号布局的自动布局生成器
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143982
N. Baha, M. Beddiaf, A. Gadiri
{"title":"GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics","authors":"N. Baha, M. Beddiaf, A. Gadiri","doi":"10.1109/GLSV.1991.143982","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143982","url":null,"abstract":"The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into leaf cells and generates their corresponding layouts. The sublayouts are then automatically placed and ready to be routed.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121139288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A poly to active region VLSI mask alignment test structure 一种多晶硅到有源区掩模对准测试结构
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143979
T. Ramesh
{"title":"A poly to active region VLSI mask alignment test structure","authors":"T. Ramesh","doi":"10.1109/GLSV.1991.143979","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143979","url":null,"abstract":"Present day CMOS technologies require continuous evaluation of the technology in terms of optimizing the design rules. Electrical monitoring of mask alignment is one such evaluation tool. A VLSI test structure for monitoring the poly to active region mask misalignment is presented. The structure is designed based on 2-micron scalable CMOS (SCMOS) design rules. The issues related to sensitivity of the measurement, and some critical design considerations are discussed.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121354398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the complexity of a fault-tolerance model for multicomputer systems 多机系统容错模型的复杂性
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143943
A. D. Oh, Hyeong-Ah Choi, A. Esfahanian
{"title":"On the complexity of a fault-tolerance model for multicomputer systems","authors":"A. D. Oh, Hyeong-Ah Choi, A. Esfahanian","doi":"10.1109/GLSV.1991.143943","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143943","url":null,"abstract":"In topological design of multicomputer systems (e.g., the hypercube), the edge- and vertex-connectivities have traditionally been used as deterministic measures of fault-tolerance. These measures have been noted to have some deficiencies and as a result several generalizations of graph connectivity have been proposed. In this paper, the authors examine some instances of the connectivity generalization proposed by Esfahanian and Hakimi, (1988). This generalization of graph connectivity can be used to model the fault-tolerance analysis of multicomputers in which any set S of the multicomputer components is considered fault free if the set S does not satisfy some given topological property rho . Using this model and different definitions of rho , the authors establish the complexity of analyzing the fault-tolerance of multicomputers.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126861027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High frequency analog circuit design using QuickChip 利用QuickChip设计高频模拟电路
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143965
S. Burns
{"title":"High frequency analog circuit design using QuickChip","authors":"S. Burns","doi":"10.1109/GLSV.1991.143965","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143965","url":null,"abstract":"The author describes analog circuit design methodologies and techniques required to optimize high frequency performance when operating near the upper frequency limit of BJT-based analog ASICs. The Tektronix QuickChip 2S ASIC array is used as the analysis and test vehicle. These techniques are illustrated using a series of examples including an actively shunt-peaked wideband amplifier and a multi-chip FM receiver as well as an analysis of the need to optimize the RC product in the manual routing of both metallizations in critical areas of the circuit.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122130318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Schematic driven layout for the custom VLSI design environment 原理图驱动布局的自定义VLSI设计环境
[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI: 10.1109/GLSV.1991.143983
J. Canaris
{"title":"Schematic driven layout for the custom VLSI design environment","authors":"J. Canaris","doi":"10.1109/GLSV.1991.143983","DOIUrl":"https://doi.org/10.1109/GLSV.1991.143983","url":null,"abstract":"The tool needs of the custom VLSI layout environment are being virtually ignored by the CAD tool community. A set of simple, schematic driven layout tools, specified to assist a human layout designer in the custom VLSI environment, is proposed in this paper. These tools include: a smart tiler; interactive channel router; and random logic layout synthesis.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124610782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信