GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics

Abstract

The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into leaf cells and generates their corresponding layouts. The sublayouts are then automatically placed and ready to be routed.<>