一种多晶硅到有源区掩模对准测试结构

[1991] Proceedings. First Great Lakes Symposium on VLSI Pub Date : 1991-03-01 DOI:10.1109/GLSV.1991.143979

T. Ramesh

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引用次数: 0

摘要

目前的CMOS技术需要在优化设计规则方面对技术进行持续评估。掩模对准的电气监测就是这样一种评估工具。提出了一种用于监测多晶硅与有源区掩模不对准的VLSI测试结构。该结构是基于2微米可扩展CMOS (SCMOS)设计规则设计的。讨论了与测量灵敏度有关的问题，以及一些关键的设计考虑。

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A poly to active region VLSI mask alignment test structure

Present day CMOS technologies require continuous evaluation of the technology in terms of optimizing the design rules. Electrical monitoring of mask alignment is one such evaluation tool. A VLSI test structure for monitoring the poly to active region mask misalignment is presented. The structure is designed based on 2-micron scalable CMOS (SCMOS) design rules. The issues related to sensitivity of the measurement, and some critical design considerations are discussed.<>

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[1991] Proceedings. First Great Lakes Symposium on VLSI

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