I/O bound binary tree layout

Abstract

The authors propose a VLSI layout strategy for a full binary tree. This layout can support more border leaf processing elements (PEs) and thus can give a higher I-O bandwidth. It is superior to the H-tree layout in terms of the number of boundary leaves. The approach uses H-tree pattern for constructing subtree layouts and then combines a number of such subtrees following standard tree style to get a larger sized tree layout. Finally at the top level H-tree layout style is used to get the overall tree layout. Different I/O bandwidths can be obtained varying the subtree height. The authors derive expression for layout area, longest link and aspect ratio of the chip. It is observed that I/O bandwidth can be significantly increased without much area overhead using this approach.<>